From nobody Sat May 4 13:31:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542716303117592.3663659145814; Tue, 20 Nov 2018 04:18:23 -0800 (PST) Received: from localhost ([::1]:33354 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gP4yq-0002YP-HG for importer@patchew.org; Tue, 20 Nov 2018 07:18:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43661) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gP4wz-0001fz-An for qemu-devel@nongnu.org; Tue, 20 Nov 2018 07:16:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gP4wx-0004zz-RG for qemu-devel@nongnu.org; Tue, 20 Nov 2018 07:16:17 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:43378) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gP4wx-0004zl-Jn for qemu-devel@nongnu.org; Tue, 20 Nov 2018 07:16:15 -0500 Received: by mail-pg1-x542.google.com with SMTP id v28so822467pgk.10 for ; Tue, 20 Nov 2018 04:16:15 -0800 (PST) Received: from cloudburst.twiddle.net ([172.56.31.89]) by smtp.gmail.com with ESMTPSA id p11sm39244346pgn.60.2018.11.20.04.16.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Nov 2018 04:16:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=z4yX/M+ZC4TDSeIM8DiZ2IxP9TzprzpB2ARLKW/YK1w=; b=Hljbffd0Jaxln+8H6xFzAg0F1xPGlKCKLRbZ+1MxnbefCns5X2r1RTYB7uOQ08WlFV r2pCsOVgCRYfHcTzR1S3y7mYsElroN5xyCOHvuXJj9mTwD5S/JcspycYDHLBPmC9IMHr sIIpWSdz+Dc2mThTFwB2U+FVlA0H7sby4J1W0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=z4yX/M+ZC4TDSeIM8DiZ2IxP9TzprzpB2ARLKW/YK1w=; b=SXoB8aKK0r6XQb8Hm0uBevq2+qj9YA5D2+pplo4/C8sVMBggdC1L4cTUPs9uCuYRCh gznoV7HcrOTlLRLUr2xrd+dT7imi1kjANpyVXp7A6n6eSvh775fLZY1XH+vj8JmEmXOE QPkAQG8d6t2uTmw2MV8W5jMx5vQ5qRpBcKa4+MIWuRewzKhFmMucIYW6sGcQ2kQptnpf iM55s+MvGqzFmOdoEjdsrxFVAiRc60RsyVAS+z5WY+1zb+EVkMJOGTEWEK/JSOYpylRA 1GSdV5FqWIRsFe3Qqz4XUfF6pjLZg0jb5uPi8zwrXD/PgyRTTcbp+TEX+NYgUyuaDGOA 1e+w== X-Gm-Message-State: AA+aEWZA8nGSFZ4lm8mxP6iIOele/iGYbmdRvPKbnS8JsnkuDR23RV6c Hbjwq2l9l9TT1Hx1ad+AKW8xu7s8YqGDlg== X-Google-Smtp-Source: AFSGD/XjKT5m5bsex7XJPCLqMxAAzQce8toywG273/omGl9m7bsg0klXzkXq61B/0IrZW0+OJgl4Hw== X-Received: by 2002:a63:d818:: with SMTP id b24mr1667486pgh.174.1542716173936; Tue, 20 Nov 2018 04:16:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 20 Nov 2018 13:15:54 +0100 Message-Id: <20181120121558.7660-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181120121558.7660-1-richard.henderson@linaro.org> References: <20181120121558.7660-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 1/5] tcg: Add TCG_TARGET_HAS_MEMORY_BSWAP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For now, defined universally as true, since we previously required backends to implement swapped memory operations. Future patches may now remove that support where it is onerous. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 2 + tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + tcg/tci/tcg-target.h | 2 + tcg/tcg-op.c | 118 ++++++++++++++++++++++++++++++++++++++- 9 files changed, 126 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 9aea1d1771..f966a4fcb3 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -137,6 +137,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 =20 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 94b3578c55..16172f73a3 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -131,6 +131,7 @@ enum { }; =20 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2441658865..b1b861f8f2 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -219,6 +219,8 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 + #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index a8222476f0..5cb8672470 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -203,6 +203,7 @@ extern bool use_mips32r2_instructions; #endif =20 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be52ad1d2e..52c1bb04b1 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -128,6 +128,7 @@ void flush_icache_range(uintptr_t start, uintptr_t stop= ); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 6f2b06a7d1..853ed6e7aa 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -135,6 +135,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_CALL_STACK_OFFSET 160 =20 #define TCG_TARGET_EXTEND_ARGS 1 +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index d8339bf010..a0ed2a3342 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -164,6 +164,7 @@ extern bool use_vis3_instructions; #define TCG_AREG0 TCG_REG_I0 =20 #define TCG_TARGET_DEFAULT_MO (0) +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 26140d78cb..086f34e69a 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -198,6 +198,8 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) We prefer consistency across hosts on this. */ #define TCG_TARGET_DEFAULT_MO (0) =20 +#define TCG_TARGET_HAS_MEMORY_BSWAP 1 + static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t = addr) { diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7a8015c5a9..56e36de7ce 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2701,25 +2701,78 @@ static void tcg_gen_req_mo(TCGBar type) =20 void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { + TCGMemOp orig_memop; + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); + + orig_memop =3D memop; + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + memop &=3D ~MO_BSWAP; + /* The bswap primitive requires zero-extended input. */ + if ((memop & MO_SSIZE) =3D=3D MO_SW) { + memop &=3D ~MO_SIGN; + } + } + gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); + + if ((orig_memop ^ memop) & MO_BSWAP) { + switch (orig_memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16_i32(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext16s_i32(val, val); + } + break; + case MO_32: + tcg_gen_bswap32_i32(val, val); + break; + default: + g_assert_not_reached(); + } + } } =20 void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { + TCGv_i32 swap =3D NULL; + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 0, 1); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); + + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + swap =3D tcg_temp_new_i32(); + switch (memop & MO_SIZE) { + case MO_16: + tcg_gen_ext16u_i32(swap, val); + tcg_gen_bswap16_i32(swap, swap); + break; + case MO_32: + tcg_gen_bswap32_i32(swap, val); + break; + default: + g_assert_not_reached(); + } + val =3D swap; + memop &=3D ~MO_BSWAP; + } + gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); + + if (swap) { + tcg_temp_free_i32(swap); + } } =20 void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + TCGMemOp orig_memop; + if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); if (memop & MO_SIGN) { @@ -2730,24 +2783,85 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, T= CGArg idx, TCGMemOp memop) return; } =20 + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 1, 0); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); + + orig_memop =3D memop; + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + memop &=3D ~MO_BSWAP; + /* The bswap primitive requires zero-extended input. */ + if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) { + memop &=3D ~MO_SIGN; + } + } + gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); + + if ((orig_memop ^ memop) & MO_BSWAP) { + switch (orig_memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16_i64(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext16s_i64(val, val); + } + break; + case MO_32: + tcg_gen_bswap32_i64(val, val); + if (orig_memop & MO_SIGN) { + tcg_gen_ext32s_i64(val, val); + } + break; + case MO_64: + tcg_gen_bswap64_i64(val, val); + break; + default: + g_assert_not_reached(); + } + } } =20 void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { - tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + TCGv_i64 swap =3D NULL; + if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); return; } =20 + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 1, 1); trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); + + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + swap =3D tcg_temp_new_i64(); + switch (memop & MO_SIZE) { + case MO_16: + tcg_gen_ext16u_i64(swap, val); + tcg_gen_bswap16_i64(swap, swap); + break; + case MO_32: + tcg_gen_ext32u_i64(swap, val); + tcg_gen_bswap32_i64(swap, swap); + break; + case MO_64: + tcg_gen_bswap64_i64(swap, val); + break; + default: + g_assert_not_reached(); + } + val =3D swap; + memop &=3D ~MO_BSWAP; + } + gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); + + if (swap) { + tcg_temp_free_i64(swap); + } } =20 static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) --=20 2.17.2 From nobody Sat May 4 13:31:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Tue, 20 Nov 2018 04:16:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 20 Nov 2018 13:15:55 +0100 Message-Id: <20181120121558.7660-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181120121558.7660-1-richard.henderson@linaro.org> References: <20181120121558.7660-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PATCH 2/5] tcg/optimize: Optimize bswap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Somehow we forgot these operations, once upon a time. This will allow immediate stores to have their bswap optimized away. Signed-off-by: Richard Henderson --- tcg/optimize.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 5dbe11c3c8..6b98ec13e6 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -353,6 +353,15 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGA= rg x, TCGArg y) CASE_OP_32_64(ext16u): return (uint16_t)x; =20 + CASE_OP_32_64(bswap16): + return bswap16(x); + + CASE_OP_32_64(bswap32): + return bswap32(x); + + case INDEX_op_bswap64_i64: + return bswap64(x); + case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: return (int32_t)x; @@ -1105,6 +1114,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(ext16s): CASE_OP_32_64(ext16u): CASE_OP_32_64(ctpop): + CASE_OP_32_64(bswap16): + CASE_OP_32_64(bswap32): + case INDEX_op_bswap64_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: --=20 2.17.2 From nobody Sat May 4 13:31:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542716523963242.06879464028736; Tue, 20 Nov 2018 04:22:03 -0800 (PST) Received: from localhost ([::1]:33380 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gP52Y-0005vq-SX for importer@patchew.org; Tue, 20 Nov 2018 07:22:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43708) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gP4x7-0001mG-53 for qemu-devel@nongnu.org; Tue, 20 Nov 2018 07:16:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gP4x4-00052Q-1T for qemu-devel@nongnu.org; Tue, 20 Nov 2018 07:16:25 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:41392) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gP4x3-000523-Q0 for qemu-devel@nongnu.org; Tue, 20 Nov 2018 07:16:21 -0500 Received: by mail-pg1-x542.google.com with SMTP id 70so826761pgh.8 for ; Tue, 20 Nov 2018 04:16:21 -0800 (PST) Received: from cloudburst.twiddle.net ([172.56.31.89]) by smtp.gmail.com with ESMTPSA id p11sm39244346pgn.60.2018.11.20.04.16.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Nov 2018 04:16:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=e3EmH68WadAw/qnOzSoJTL4P+UKvkirDo0hQAqlSqhk=; b=PAk6vUQAdGa5Rx+w8evqlbdzlQwwKkl5Z6qDHBTiLX2XdrSLQyzLZYAMDNhTHipmfG ZGR/HcHXp9599aEKwck9C+OlhZkXzdq+KRCUG2yBpb6AqT5iP/FgVAfhljdCrteI5roU vHZ1qrnSyXzxNboupQeXXpJXtOORkeC38kx0I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e3EmH68WadAw/qnOzSoJTL4P+UKvkirDo0hQAqlSqhk=; b=LYhB/fnSjQzmB6ncfQnqHLhyGM8PhuGdRrPY424VNu/gyMNJvH6P0NfPvju/f9VF9k ESVTttKejyhD/wr8U6uDK/XachY+1yBbQ+qJGNCg8tmc4qgp7JXKeb5fMLCqwsmmUfMi sN474C2G2nMoed7PW1HlIqgmomIqP156AOALAWgSpFxQtxugnkZ6pF0tb0C46axWcwHn jCkVKXd+afEiIrx2CjhGxQnrB/JXeY1zFpIozDtbv8gU5eRxfmIY5HS7tc9APBzssmnP QXuvn6d7dCpIUAT4X4jWOtmNFjX3txo4ogv9EK3x/M1pQAiw/CdPvkNP3HRM+kOvGfaP hV+g== X-Gm-Message-State: AGRZ1gJBNc9EZnEicRaGC4B89NrzeaUz3HmP5vq8Yq4pKx1ULutgdsl5 sZFoYisTsAvqzmjXnPAHHmzZ4pb1LHBuJA== X-Google-Smtp-Source: AJdET5e0aih3wGbx8keCoMKiGjzWqBJ7qOziGS3s4Uu/6BMafZrM5ZK0enND9VHrjQzTMKRsE1B9Rg== X-Received: by 2002:a62:9402:: with SMTP id m2mr1944152pfe.34.1542716180477; Tue, 20 Nov 2018 04:16:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 20 Nov 2018 13:15:56 +0100 Message-Id: <20181120121558.7660-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181120121558.7660-1-richard.henderson@linaro.org> References: <20181120121558.7660-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 3/5] tcg/i386: Set TCG_TARGET_HAS_MEMORY_BSWAP with have_movbe X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows us to remove some code from the backend, allowing the generic code to emit any extra bswaps. This does not quite allow all of the cleanup that should be possible, as we still must take care of i386 storing bytes from non 'q' registers. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 3 +- tcg/i386/tcg-target.inc.c | 112 ++++++++++++-------------------------- 2 files changed, 37 insertions(+), 78 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b1b861f8f2..ed2d5d4441 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -101,6 +101,7 @@ extern bool have_bmi1; extern bool have_popcnt; extern bool have_avx1; extern bool have_avx2; +extern bool have_movbe; =20 /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 @@ -219,7 +220,7 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe =20 #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 436195894b..14e1cf9eee 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -154,13 +154,12 @@ bool have_bmi1; bool have_popcnt; bool have_avx1; bool have_avx2; +bool have_movbe; =20 #ifdef CONFIG_CPUID_H -static bool have_movbe; static bool have_bmi2; static bool have_lzcnt; #else -# define have_movbe 0 # define have_bmi2 0 # define have_lzcnt 0 #endif @@ -1884,12 +1883,11 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, int seg, TCGMemOp memop) { - const TCGMemOp real_bswap =3D memop & MO_BSWAP; - TCGMemOp bswap =3D real_bswap; + bool need_bswap =3D memop & MO_BSWAP; int movop =3D OPC_MOVL_GvEv; =20 - if (have_movbe && real_bswap) { - bswap =3D 0; + if (need_bswap) { + tcg_debug_assert(have_movbe); movop =3D OPC_MOVBE_GyMy; } =20 @@ -1903,46 +1901,41 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, base, index, 0, ofs); break; case MO_UW: - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, + if (!need_bswap) { + tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, base, index, 0, ofs); - if (real_bswap) { - tcg_out_rolw_8(s, datalo); + } else if (datalo !=3D base && datalo !=3D index) { + tcg_out_movi(s, TCG_TYPE_I32, datalo, 0); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, + datalo, base, index, 0, ofs); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, + datalo, base, index, 0, ofs); + tcg_out_ext16u(s, datalo, datalo); } break; case MO_SW: - if (real_bswap) { - if (have_movbe) { - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + se= g, - datalo, base, index, 0, ofs); - } else { - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); - tcg_out_rolw_8(s, datalo); - } - tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo); - } else { + if (!need_bswap) { tcg_out_modrm_sib_offset(s, OPC_MOVSWL + P_REXW + seg, datalo, base, index, 0, ofs); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, + datalo, base, index, 0, ofs); + tcg_out_ext16s(s, datalo, datalo, P_REXW); } break; case MO_UL: tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, o= fs); - if (bswap) { - tcg_out_bswap32(s, datalo); - } break; #if TCG_TARGET_REG_BITS =3D=3D 64 case MO_SL: - if (real_bswap) { - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - if (bswap) { - tcg_out_bswap32(s, datalo); - } - tcg_out_ext32s(s, datalo, datalo); - } else { + if (!need_bswap) { tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo, base, index, 0, ofs); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + seg, datalo, + base, index, 0, ofs); + tcg_out_ext32s(s, datalo, datalo); } break; #endif @@ -1950,12 +1943,9 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TC= GReg datalo, TCGReg datahi, if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, base, index, 0, ofs); - if (bswap) { - tcg_out_bswap64(s, datalo); - } } else { - if (real_bswap) { - int t =3D datalo; + if (need_bswap) { + TCGReg t =3D datalo; datalo =3D datahi; datahi =3D t; } @@ -1970,14 +1960,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); } - if (bswap) { - tcg_out_bswap32(s, datalo); - tcg_out_bswap32(s, datahi); - } } break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -2053,17 +2039,11 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, TCGReg base, intptr_t ofs, int seg, TCGMemOp memop) { - /* ??? Ideally we wouldn't need a scratch register. For user-only, - we could perform the bswap twice to restore the original value - instead of moving to the scratch. But as it is, the L constraint - means that TCG_REG_L0 is definitely free here. */ - const TCGReg scratch =3D TCG_REG_L0; - const TCGMemOp real_bswap =3D memop & MO_BSWAP; - TCGMemOp bswap =3D real_bswap; + bool need_bswap =3D memop & MO_BSWAP; int movop =3D OPC_MOVL_EvGv; =20 - if (have_movbe && real_bswap) { - bswap =3D 0; + if (need_bswap) { + tcg_debug_assert(have_movbe); movop =3D OPC_MOVBE_MyGy; } =20 @@ -2072,46 +2052,24 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. Use the scratch register if necessary. */ if (TCG_TARGET_REG_BITS =3D=3D 32 && datalo >=3D 4) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - datalo =3D scratch; + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_L0, datalo); + datalo =3D TCG_REG_L0; } tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, datalo, base, ofs); break; case MO_16: - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_rolw_8(s, scratch); - datalo =3D scratch; - } tcg_out_modrm_offset(s, movop + P_DATA16 + seg, datalo, base, ofs); break; case MO_32: - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_bswap32(s, scratch); - datalo =3D scratch; - } tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs); break; case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo); - tcg_out_bswap64(s, scratch); - datalo =3D scratch; - } tcg_out_modrm_offset(s, movop + P_REXW + seg, datalo, base, of= s); - } else if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); - tcg_out_bswap32(s, scratch); - tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, of= s); - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_bswap32(s, scratch); - tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, of= s+4); } else { - if (real_bswap) { - int t =3D datalo; + if (need_bswap) { + TCGReg t =3D datalo; datalo =3D datahi; datahi =3D t; } @@ -2120,7 +2078,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, } break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 --=20 2.17.2 From nobody Sat May 4 13:31:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 20 Nov 2018 04:16:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 20 Nov 2018 13:15:57 +0100 Message-Id: <20181120121558.7660-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181120121558.7660-1-richard.henderson@linaro.org> References: <20181120121558.7660-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH 4/5] tcg/aarch64: Set TCG_TARGET_HAS_MEMORY_BSWAP to false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows us to remove some code from the backend, allowing the generic code to emit any extra bswaps. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 63 ++++++++---------------------------- 2 files changed, 14 insertions(+), 51 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index f966a4fcb3..ef9e9084b2 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -137,7 +137,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 =20 #define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 083592a4d7..784c31d783 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1383,9 +1383,6 @@ static void * const qemu_ld_helpers[16] =3D { [MO_LEUW] =3D helper_le_lduw_mmu, [MO_LEUL] =3D helper_le_ldul_mmu, [MO_LEQ] =3D helper_le_ldq_mmu, - [MO_BEUW] =3D helper_be_lduw_mmu, - [MO_BEUL] =3D helper_be_ldul_mmu, - [MO_BEQ] =3D helper_be_ldq_mmu, }; =20 /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, @@ -1397,9 +1394,6 @@ static void * const qemu_st_helpers[16] =3D { [MO_LEUW] =3D helper_le_stw_mmu, [MO_LEUL] =3D helper_le_stl_mmu, [MO_LEQ] =3D helper_le_stq_mmu, - [MO_BEUW] =3D helper_be_stw_mmu, - [MO_BEUL] =3D helper_be_stl_mmu, - [MO_BEQ] =3D helper_be_stq_mmu, }; =20 static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target) @@ -1421,7 +1415,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); tcg_out_adr(s, TCG_REG_X3, lb->raddr); - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_call(s, qemu_ld_helpers[opc & MO_SIZE]); if (opc & MO_SIGN) { tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0); } else { @@ -1444,7 +1438,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_mov(s, size =3D=3D MO_64, TCG_REG_X2, lb->datalo_reg); tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi); tcg_out_adr(s, TCG_REG_X4, lb->raddr); - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE]); tcg_out_goto(s, lb->raddr); } =20 @@ -1544,8 +1538,6 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= MemOp memop, TCGType ext, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - const TCGMemOp bswap =3D memop & MO_BSWAP; - switch (memop & MO_SSIZE) { case MO_UB: tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); @@ -1556,43 +1548,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGMemOp memop, TCGType ext, break; case MO_UW: tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev16(s, data_r, data_r); - } break; case MO_SW: - if (bswap) { - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); - tcg_out_rev16(s, data_r, data_r); - tcg_out_sxt(s, ext, MO_16, data_r, data_r); - } else { - tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), - data_r, addr_r, otype, off_r); - } + tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), + data_r, addr_r, otype, off_r); break; case MO_UL: tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev32(s, data_r, data_r); - } break; case MO_SL: - if (bswap) { - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); - tcg_out_rev32(s, data_r, data_r); - tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r); - } else { - tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); - } + tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); break; case MO_Q: tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev64(s, data_r, data_r); - } break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1600,35 +1571,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGMemOp memop, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - const TCGMemOp bswap =3D memop & MO_BSWAP; - switch (memop & MO_SIZE) { case MO_8: tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); break; case MO_16: - if (bswap && data_r !=3D TCG_REG_XZR) { - tcg_out_rev16(s, TCG_REG_TMP, data_r); - data_r =3D TCG_REG_TMP; - } tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r); break; case MO_32: - if (bswap && data_r !=3D TCG_REG_XZR) { - tcg_out_rev32(s, TCG_REG_TMP, data_r); - data_r =3D TCG_REG_TMP; - } tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r); break; case MO_64: - if (bswap && data_r !=3D TCG_REG_XZR) { - tcg_out_rev64(s, TCG_REG_TMP, data_r); - data_r =3D TCG_REG_TMP; - } tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1637,6 +1594,9 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, { TCGMemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + + tcg_debug_assert(!(memop & MO_BSWAP)); + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; @@ -1662,6 +1622,9 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, { TCGMemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + + tcg_debug_assert(!(memop & MO_BSWAP)); + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; --=20 2.17.2 From nobody Sat May 4 13:31:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542716441194325.4382346637908; Tue, 20 Nov 2018 04:20:41 -0800 (PST) Received: from localhost ([::1]:33366 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gP51E-0004pv-2B for importer@patchew.org; Tue, 20 Nov 2018 07:20:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43738) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gP4xD-0001ov-K2 for qemu-devel@nongnu.org; Tue, 20 Nov 2018 07:16:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gP4xC-00056I-4v for qemu-devel@nongnu.org; Tue, 20 Nov 2018 07:16:31 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:40255) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gP4xB-000566-SV for qemu-devel@nongnu.org; Tue, 20 Nov 2018 07:16:30 -0500 Received: by mail-pg1-x544.google.com with SMTP id z10so830985pgp.7 for ; Tue, 20 Nov 2018 04:16:29 -0800 (PST) Received: from cloudburst.twiddle.net ([172.56.31.89]) by smtp.gmail.com with ESMTPSA id p11sm39244346pgn.60.2018.11.20.04.16.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Nov 2018 04:16:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s3murmLKiphxCfNccSYceQQGbVGL9qVHXXjcQZfEjxM=; b=G8HS0pxc/6M7caGC5dvlHw1t9BK1cVZDq+EItLBLqCYJ/It7OPxPtV5eVS8MuR+MhH xO2ZtlQy0qSvL7FTGXDWd2J+bN7yZc531iS8iac789c54w1XorEcXhxDkFQWYTf7vjZv +8kkDC/fe6R12G7eh+0yf+M+pTCObbVbDaXtg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s3murmLKiphxCfNccSYceQQGbVGL9qVHXXjcQZfEjxM=; b=Idho4o3XK08sRi7ZYJdd4hJTmr9+fSjF0GXEeWYYrfcmYoW+rxMAL1wBh8i7JYh14R oF0bO1tXqf9bPp9UNGktqh/8kLYFbNq7e611vFm5d68eSHFRLMoj/wKgGB4RtAcYs9Yy 0T9Vz3aNLesbfjuhLcBcZf8T1VV66Twg3fnoqrqmOhatuHitP7lnFmq4CmfuOb9Ul4lI nh8Q5HKdGQWBsF7DUbvxiQaj9dXik5ylwtkeh8p/YbTUN1u/qQ0nouWnuSDpmol2yuCL 1Vq4si6rfKMRrnF4GKUNuotc3H1GI2eyyN7ClByYkAPBjavhuQV9KVlI2ZXh1W/VxtHb vQLQ== X-Gm-Message-State: AA+aEWbGIeXRGz5yJOIhaEEd1PGAC6uniGA3+ugJUAWOISYZz+FXzx05 pIuHRJ2tzRj0MmrWVgZm1Y+P8ouQUPHOHA== X-Google-Smtp-Source: AFSGD/UcYPr088pBp6J0mfzhgJj2DuhXXIHeupU+QkTlkIrqSKN4RlrmkUP3k2gcXBVHtObPGm2Baw== X-Received: by 2002:a63:9f19:: with SMTP id g25mr1665047pge.327.1542716188350; Tue, 20 Nov 2018 04:16:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 20 Nov 2018 13:15:58 +0100 Message-Id: <20181120121558.7660-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181120121558.7660-1-richard.henderson@linaro.org> References: <20181120121558.7660-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 5/5] tcg/arm: Set TCG_TARGET_HAS_MEMORY_BSWAP to false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows us to remove some code from the backend, allowing the generic code to emit any extra bswaps. It also allows us to avoid reserving an extra register for CONFIG_USER_ONLY. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.inc.c | 198 ++++++++++----------------------------- 2 files changed, 48 insertions(+), 152 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 16172f73a3..a6f7be5483 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -131,7 +131,7 @@ enum { }; =20 #define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index e1fbf465cb..0043454d6b 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -285,11 +285,10 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, case 's': ct->ct |=3D TCG_CT_REG; ct->u.regs =3D 0xffff; - /* r0-r2 will be overwritten when reading the tlb entry (softmmu o= nly) - and r0-r1 doing the byte swapping, so don't use these. */ +#if defined(CONFIG_SOFTMMU) + /* r0-r2 will be overwritten when reading the tlb entry. */ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); -#if defined(CONFIG_SOFTMMU) /* Avoid clashes with registers being used for helper args */ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); #if TARGET_LONG_BITS =3D=3D 64 @@ -870,21 +869,6 @@ static inline void tcg_out_ext16u(TCGContext *s, int c= ond, } } =20 -static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int r= n) -{ - if (use_armv6_instructions) { - /* revsh */ - tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24)); - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_ASR(16)); - tcg_out_dat_reg(s, cond, ARITH_ORR, - rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8)); - } -} - static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { @@ -900,22 +884,6 @@ static inline void tcg_out_bswap16(TCGContext *s, int = cond, int rd, int rn) } } =20 -/* swap the two low bytes assuming that the two high input bytes and the - two high output bit can hold any value. */ -static inline void tcg_out_bswap16st(TCGContext *s, int cond, int rd, int = rn) -{ - if (use_armv6_instructions) { - /* rev16 */ - tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, rn, SHIFT_IMM_LSR(8)); - tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, 0xff= ); - tcg_out_dat_reg(s, cond, ARITH_ORR, - rd, TCG_REG_TMP, rn, SHIFT_IMM_LSL(8)); - } -} - static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { @@ -1410,9 +1378,9 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) icache usage. For pre-armv6, use the signed helpers since we do not have a single insn sign-extend. */ if (use_armv6_instructions) { - func =3D qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]; + func =3D qemu_ld_helpers[opc & MO_SIZE]; } else { - func =3D qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]; + func =3D qemu_ld_helpers[opc & MO_SSIZE]; if (opc & MO_SIGN) { opc =3D MO_UL; } @@ -1487,7 +1455,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); =20 /* Tail-call to the helper, which will return to the fast path. */ - tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); } #endif /* SOFTMMU */ =20 @@ -1495,8 +1463,6 @@ static inline void tcg_out_qemu_ld_index(TCGContext *= s, TCGMemOp opc, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addend) { - TCGMemOp bswap =3D opc & MO_BSWAP; - switch (opc & MO_SSIZE) { case MO_UB: tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend); @@ -1506,49 +1472,30 @@ static inline void tcg_out_qemu_ld_index(TCGContext= *s, TCGMemOp opc, break; case MO_UW: tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend); - if (bswap) { - tcg_out_bswap16(s, COND_AL, datalo, datalo); - } break; case MO_SW: - if (bswap) { - tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend); - tcg_out_bswap16s(s, COND_AL, datalo, datalo); - } else { - tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend); - } + tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend); break; case MO_UL: - default: tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); - if (bswap) { - tcg_out_bswap32(s, COND_AL, datalo, datalo); - } break; case MO_Q: - { - TCGReg dl =3D (bswap ? datahi : datalo); - TCGReg dh =3D (bswap ? datalo : datahi); - - /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions - && (dl & 1) =3D=3D 0 && dh =3D=3D dl + 1) { - tcg_out_ldrd_r(s, COND_AL, dl, addrlo, addend); - } else if (dl !=3D addend) { - tcg_out_ld32_rwb(s, COND_AL, dl, addend, addrlo); - tcg_out_ld32_12(s, COND_AL, dh, addend, 4); - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP, - addend, addrlo, SHIFT_IMM_LSL(0)); - tcg_out_ld32_12(s, COND_AL, dl, TCG_REG_TMP, 0); - tcg_out_ld32_12(s, COND_AL, dh, TCG_REG_TMP, 4); - } - if (bswap) { - tcg_out_bswap32(s, COND_AL, dl, dl); - tcg_out_bswap32(s, COND_AL, dh, dh); - } + /* Avoid ldrd for user-only emulation, to handle unaligned. */ + if (USING_SOFTMMU && use_armv6_instructions + && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { + tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); + } else if (datalo !=3D addend) { + tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo); + tcg_out_ld32_12(s, COND_AL, datahi, addend, 4); + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP, + addend, addrlo, SHIFT_IMM_LSL(0)); + tcg_out_ld32_12(s, COND_AL, datalo, TCG_REG_TMP, 0); + tcg_out_ld32_12(s, COND_AL, datahi, TCG_REG_TMP, 4); } break; + default: + g_assert_not_reached(); } } =20 @@ -1556,8 +1503,6 @@ static inline void tcg_out_qemu_ld_direct(TCGContext = *s, TCGMemOp opc, TCGReg datalo, TCGReg datahi, TCGReg addrlo) { - TCGMemOp bswap =3D opc & MO_BSWAP; - switch (opc & MO_SSIZE) { case MO_UB: tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0); @@ -1567,47 +1512,28 @@ static inline void tcg_out_qemu_ld_direct(TCGContex= t *s, TCGMemOp opc, break; case MO_UW: tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - if (bswap) { - tcg_out_bswap16(s, COND_AL, datalo, datalo); - } break; case MO_SW: - if (bswap) { - tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - tcg_out_bswap16s(s, COND_AL, datalo, datalo); - } else { - tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); - } + tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); break; case MO_UL: - default: tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - if (bswap) { - tcg_out_bswap32(s, COND_AL, datalo, datalo); - } break; case MO_Q: - { - TCGReg dl =3D (bswap ? datahi : datalo); - TCGReg dh =3D (bswap ? datalo : datahi); - - /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions - && (dl & 1) =3D=3D 0 && dh =3D=3D dl + 1) { - tcg_out_ldrd_8(s, COND_AL, dl, addrlo, 0); - } else if (dl =3D=3D addrlo) { - tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4); - tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0); - } else { - tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0); - tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4); - } - if (bswap) { - tcg_out_bswap32(s, COND_AL, dl, dl); - tcg_out_bswap32(s, COND_AL, dh, dh); - } + /* Avoid ldrd for user-only emulation, to handle unaligned. */ + if (USING_SOFTMMU && use_armv6_instructions + && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { + tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); + } else if (datalo =3D=3D addrlo) { + tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); + tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); + } else { + tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); } break; + default: + g_assert_not_reached(); } } =20 @@ -1628,6 +1554,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); oi =3D *args++; opc =3D get_memop(oi); + tcg_debug_assert(!(opc & MO_BSWAP)); =20 #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); @@ -1656,44 +1583,28 @@ static inline void tcg_out_qemu_st_index(TCGContext= *s, int cond, TCGMemOp opc, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addend) { - TCGMemOp bswap =3D opc & MO_BSWAP; - switch (opc & MO_SIZE) { case MO_8: tcg_out_st8_r(s, cond, datalo, addrlo, addend); break; case MO_16: - if (bswap) { - tcg_out_bswap16st(s, cond, TCG_REG_R0, datalo); - tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend); - } else { - tcg_out_st16_r(s, cond, datalo, addrlo, addend); - } + tcg_out_st16_r(s, cond, datalo, addrlo, addend); break; case MO_32: - default: - if (bswap) { - tcg_out_bswap32(s, cond, TCG_REG_R0, datalo); - tcg_out_st32_r(s, cond, TCG_REG_R0, addrlo, addend); - } else { - tcg_out_st32_r(s, cond, datalo, addrlo, addend); - } + tcg_out_st32_r(s, cond, datalo, addrlo, addend); break; case MO_64: /* Avoid strd for user-only emulation, to handle unaligned. */ - if (bswap) { - tcg_out_bswap32(s, cond, TCG_REG_R0, datahi); - tcg_out_st32_rwb(s, cond, TCG_REG_R0, addend, addrlo); - tcg_out_bswap32(s, cond, TCG_REG_R0, datalo); - tcg_out_st32_12(s, cond, TCG_REG_R0, addend, 4); - } else if (USING_SOFTMMU && use_armv6_instructions - && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { + if (USING_SOFTMMU && use_armv6_instructions + && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_r(s, cond, datalo, addrlo, addend); } else { tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); tcg_out_st32_12(s, cond, datahi, addend, 4); } break; + default: + g_assert_not_reached(); } } =20 @@ -1701,44 +1612,28 @@ static inline void tcg_out_qemu_st_direct(TCGContex= t *s, TCGMemOp opc, TCGReg datalo, TCGReg datahi, TCGReg addrlo) { - TCGMemOp bswap =3D opc & MO_BSWAP; - switch (opc & MO_SIZE) { case MO_8: tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0); break; case MO_16: - if (bswap) { - tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0); - } else { - tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); - } + tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); break; case MO_32: - default: - if (bswap) { - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0); - } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - } + tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); break; case MO_64: /* Avoid strd for user-only emulation, to handle unaligned. */ - if (bswap) { - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0); - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 4); - } else if (USING_SOFTMMU && use_armv6_instructions - && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { + if (USING_SOFTMMU && use_armv6_instructions + && (datalo & 1) =3D=3D 0 && datahi =3D=3D datalo + 1) { tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); } else { tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); } break; + default: + g_assert_not_reached(); } } =20 @@ -1759,6 +1654,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); oi =3D *args++; opc =3D get_memop(oi); + tcg_debug_assert(!(opc & MO_BSWAP)); =20 #ifdef CONFIG_SOFTMMU mem_index =3D get_mmuidx(oi); --=20 2.17.2