From nobody Thu Nov 6 18:28:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542367219321182.098180922692; Fri, 16 Nov 2018 03:20:19 -0800 (PST) Received: from localhost ([::1]:44152 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gNcAb-0008N2-Qp for importer@patchew.org; Fri, 16 Nov 2018 06:20:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34269) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gNbrD-0008Sy-EG for qemu-devel@nongnu.org; Fri, 16 Nov 2018 06:00:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gNbr7-0000c1-IJ for qemu-devel@nongnu.org; Fri, 16 Nov 2018 06:00:15 -0500 Received: from 18.mo3.mail-out.ovh.net ([87.98.172.162]:49915) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gNbr3-0000QT-8O for qemu-devel@nongnu.org; Fri, 16 Nov 2018 06:00:06 -0500 Received: from player734.ha.ovh.net (unknown [10.109.160.40]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id 13A301E9E3B for ; Fri, 16 Nov 2018 12:00:01 +0100 (CET) Received: from kaod.org (lfbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player734.ha.ovh.net (Postfix) with ESMTPSA id B8D2A280104; Fri, 16 Nov 2018 11:59:55 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Fri, 16 Nov 2018 11:57:18 +0100 Message-Id: <20181116105729.23240-26-clg@kaod.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181116105729.23240-1-clg@kaod.org> References: <20181116105729.23240-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11758898630173363174 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrleejgddvtdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 87.98.172.162 Subject: [Qemu-devel] [PATCH v5 25/36] spapr: set the interrupt presenter at reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Currently, the interrupt presenter of the VPCU is set at realize time. Setting it at reset will become useful when the new machine supporting both interrupt modes is introduced. In this machine, the interrupt mode is chosen at CAS time and activated after a reset. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/spapr_cpu_core.h | 2 ++ hw/ppc/spapr_cpu_core.c | 26 ++++++++++++++++++++++++++ hw/ppc/spapr_irq.c | 11 +++++++++++ 3 files changed, 39 insertions(+) diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_cor= e.h index 9e2821e4b31f..fc8ea9021656 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -53,4 +53,6 @@ static inline sPAPRCPUState *spapr_cpu_state(PowerPCCPU *= cpu) return (sPAPRCPUState *)cpu->machine_data; } =20 +void spapr_cpu_core_set_intc(PowerPCCPU *cpu, const char *intc_type); + #endif diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 1811cd48db90..529de0b6b9c8 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -398,3 +398,29 @@ static const TypeInfo spapr_cpu_core_type_infos[] =3D { }; =20 DEFINE_TYPES(spapr_cpu_core_type_infos) + +typedef struct ForeachFindIntCArgs { + const char *intc_type; + Object *intc; +} ForeachFindIntCArgs; + +static int spapr_cpu_core_find_intc(Object *child, void *opaque) +{ + ForeachFindIntCArgs *args =3D opaque; + + if (object_dynamic_cast(child, args->intc_type)) { + args->intc =3D child; + } + + return args->intc !=3D NULL; +} + +void spapr_cpu_core_set_intc(PowerPCCPU *cpu, const char *intc_type) +{ + ForeachFindIntCArgs args =3D { intc_type, NULL }; + + object_child_foreach(OBJECT(cpu), spapr_cpu_core_find_intc, &args); + g_assert(args.intc); + + cpu->intc =3D args.intc; +} diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 984c6d60cd9f..969efad7e6e9 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -218,6 +218,11 @@ static int spapr_irq_post_load_xics(sPAPRMachineState = *spapr, int version_id) =20 static void spapr_irq_reset_xics(sPAPRMachineState *spapr, Error **errp) { + CPUState *cs; + + CPU_FOREACH(cs) { + spapr_cpu_core_set_intc(POWERPC_CPU(cs), spapr->icp_type); + } } =20 #define SPAPR_IRQ_XICS_NR_IRQS 0x1000 @@ -370,6 +375,12 @@ static int spapr_irq_post_load_xive(sPAPRMachineState = *spapr, int version_id) =20 static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp) { + CPUState *cs; + + CPU_FOREACH(cs) { + spapr_cpu_core_set_intc(POWERPC_CPU(cs), spapr->xive_tctx_type); + } + spapr_xive_mmio_map(spapr->xive); } =20 --=20 2.17.2