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[176.87.105.26]) by smtp.gmail.com with ESMTPSA id j124-v6sm2715978wmb.1.2018.11.13.10.02.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Nov 2018 10:02:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CVcvIslv5WWkfBYxl9Mw9FAOSkXdpfKXat0+V0xS4Bs=; b=bOpPllLV9MWbjmlwJqqTv01jVkpgO1z6WpqhAbgo07bAZnS0oEPnENCSFC46hvxde9 mFZ9JzAUlVISo914WF54H7XMkUI5PEzZFvmjRFBq8d2S0S5N9wCJFyzS4WcXGEPU7LQi qxSlfz/k+uAZC9g+AFU3J7i7PutMxoEXBjVUQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CVcvIslv5WWkfBYxl9Mw9FAOSkXdpfKXat0+V0xS4Bs=; b=txe+VdZAIXRewWHyiP67XYQosu9Fz5eLjtiIbaofayqOJxaweJtO/WxeF6DkD7hxsV 67NmU7/YSdCHuJmYa7dmJVmh/s1CicmQ+mWCIubQY/N5wT8J4HT4xTUJSgQ1FCxCu9KI w6oOH1HXl9wsZbnGUFNVTngL+WIPXpSt4SfQXtHEeB6jbzPxMU5KPO5wb5L90nS61w3C 3wUmbsLqNdcV0bRI3wEb2+uqSM+8rafHAkOMORAPy153C5rPXWfNX7DRUeYTCm1z2i2/ Y5JffId48mqUeDDdSp+HUkko91NGOTSawwtOtKC6YfsoWU3LDAz+m4Fn74elR+JajBrr 7zBw== X-Gm-Message-State: AGRZ1gIZLL3VgB3893bzYG4pyDouSyqcm5HhKZeZ/7CcLa9h2l4nhH5D 7fmwGU42ENfcwHGn8zrtdKHtin2IQjuY1A== X-Google-Smtp-Source: AJdET5eXF4HYyqpoCWVlvbGb5NNVBDFxCLZIrpvFR+ObJwl9icWGumNseDtMfOrQcmTHGnWvqf6nQA== X-Received: by 2002:a1c:d14d:: with SMTP id i74mr1971100wmg.100.1542132179312; Tue, 13 Nov 2018 10:02:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 13 Nov 2018 19:01:54 +0100 Message-Id: <20181113180154.17903-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181113180154.17903-1-richard.henderson@linaro.org> References: <20181113180154.17903-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v5 4/4] target/arm: Fill in ARMISARegisters for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index bc0badf53d..bd51eb43c8 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -44,7 +44,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ah= cf) * and then query that CPU for the relevant ID registers. */ int err =3D 0, fdarray[3]; - uint32_t midr, id_pfr0, mvfr1; + uint32_t midr, id_pfr0; uint64_t features =3D 0; =20 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -71,9 +71,39 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) =20 err |=3D read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); err |=3D read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, = 0)); - err |=3D read_sys_reg32(fdarray[2], &mvfr1, + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM_CP15_REG32(0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM_CP15_REG32(0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM_CP15_REG32(0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM_CP15_REG32(0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM_CP15_REG32(0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM_CP15_REG32(0, 0, 2, 5)); + if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM_CP15_REG32(0, 0, 2, 7))) { + /* + * Older kernels don't support reading ID_ISAR6. This register was + * only introduced in ARMv8, so we can assume that it is zero on a + * CPU that a kernel this old is running on. + */ + ahcf->isar.id_isar6 =3D 0; + } + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); + /* + * FIXME: There is not yet a way to read MVFR2. + * Fortunately there is not yet anything in there that affects migrati= on. + */ =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 @@ -95,13 +125,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) if (extract32(id_pfr0, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_THUMB2EE); } - if (extract32(mvfr1, 20, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 20, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } - if (extract32(mvfr1, 12, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(mvfr1, 28, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 28, 4) =3D=3D 1) { /* FMAC support implies VFPv4 */ set_feature(&features, ARM_FEATURE_VFP4); } --=20 2.17.2