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[176.87.105.26]) by smtp.gmail.com with ESMTPSA id j124-v6sm2715978wmb.1.2018.11.13.10.02.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Nov 2018 10:02:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TK0Mu/aguozz4Q5UAQWbHigk/WZ2HXR6efE27bzs4U0=; b=ew4KVsNJua9Ss1G2RV5awkEvEbUBBN9Jfq8wOovv5lmgN/fMvdBxG+tCAO4YPLznP+ kgYhb3zEs/q9kbe4rkTEedL6N8fTgYsx87Oog2b7OPnv+2h6ttu9JLx/sSBYcJlTHzy6 +kf6STMMERfbGMnGLkW6UmW3/JsGvr7h8+MJw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TK0Mu/aguozz4Q5UAQWbHigk/WZ2HXR6efE27bzs4U0=; b=KyB9UUYKHrluTI1bSl0E/vKBpmb0rEacyz+DwHWRx2ffbmHqd9XagVOKknbD6esUry EczZqkcipOcsCI32XAj2lNVzwbinfvyZcPq8cY2pCI6xL6uageW2zT4oG2Pnke8Jh9Bp gUey6+QhStTuUQ/krPKvhyhzRrk235+h6xfBQnOgxhcmJYluuIk/eLAVZjEATp2UC6UP XrRlUdn+5ctJhXGGUdugThWZOG9DaAzm8haCoVdgdGxjCzsI8X8Hzxsu+2/SsubSpUOn ztiXsqrCMmAo7vsR/SVxMK35OpfO+gFRjX5ppgP5X4sWUwYMRNtkyrfE1LUe7qKlqzhK p/kg== X-Gm-Message-State: AGRZ1gI7SFOd9ZmPPXudlJ/vFva98zaZJiacZCjD6tgW85emP8yPbPjQ zMGdOXKZF8dZEdSZJ1BSXiwJ4brZu5K8Wg== X-Google-Smtp-Source: AJdET5dUcvOY72NT6mkOXUOt6CJR506SeAdiloiWC/VEmgkPdThata/OIuq02TfRaJivYmuEbygZHA== X-Received: by 2002:a1c:be11:: with SMTP id o17mr2165068wmf.111.1542132167946; Tue, 13 Nov 2018 10:02:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 13 Nov 2018 19:01:51 +0100 Message-Id: <20181113180154.17903-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181113180154.17903-1-richard.henderson@linaro.org> References: <20181113180154.17903-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v5 1/4] target/arm: Install ARMISARegisters from kvm host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ID registers are replacing (some of) the feature bits. We need (some of) these values to determine the set of data to be handled during migration. Signed-off-by: Richard Henderson --- target/arm/kvm_arm.h | 1 + target/arm/kvm.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 21c0129da2..6393455b1d 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -183,6 +183,7 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); * by asking the host kernel) */ typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; uint64_t features; uint32_t target; const char *dtb_compatible; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 09a86e2820..44dd0ce6ce 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -158,6 +158,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) =20 cpu->kvm_target =3D arm_host_cpu_features.target; cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; + cpu->isar =3D arm_host_cpu_features.isar; env->features =3D arm_host_cpu_features.features; } =20 --=20 2.17.2 From nobody Thu May 16 08:04:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542133282424642.0158222357245; Tue, 13 Nov 2018 10:21:22 -0800 (PST) Received: from localhost ([::1]:55604 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMdJN-0008MM-EP for importer@patchew.org; Tue, 13 Nov 2018 13:21:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57904) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMdEC-0003DO-UV for qemu-devel@nongnu.org; Tue, 13 Nov 2018 13:15:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMd1c-00081D-Ct for qemu-devel@nongnu.org; Tue, 13 Nov 2018 13:02:57 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:46347) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gMd1c-0007xe-4L for qemu-devel@nongnu.org; Tue, 13 Nov 2018 13:02:56 -0500 Received: by mail-wr1-x442.google.com with SMTP id l9so1486128wrt.13 for ; Tue, 13 Nov 2018 10:02:51 -0800 (PST) Received: from cloudburst.twiddle.net (26.red-176-87-105.dynamicip.rima-tde.net. [176.87.105.26]) by smtp.gmail.com with ESMTPSA id j124-v6sm2715978wmb.1.2018.11.13.10.02.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Nov 2018 10:02:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EfAiDKdj8MJve7c/yYaz1b7RcIsaOXjic/PkLWMwso4=; b=c72eDAP6llOj3+5j+0Q0Gv039/C4tLv2r0BRZrHhz8opYGV5jOja34Q3mlyF88OI8v 00D0m5+qon25XS6aeTFWCoXP/+Wa69lMRzWcJIlqKqX4KsBy0Ro5WPJVLhc2c3uSPq5g EV6QSN07CSIE2v1oLxU2QZ8/CoIEBGf9CzfMM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EfAiDKdj8MJve7c/yYaz1b7RcIsaOXjic/PkLWMwso4=; b=PIf1kyO/zWXBrkOPjRecrG94k1TPn7ADx+yk6Dc7bPigjvZE3iq68IVSBqo9dDjnBq VEgTTDRMoKh/kUTrbVGPdT6E9tt6XgwaNKzWwFcbXWDt5UPqqKW9rUkJQVHmChXAEfxQ dly1APfdRhTwrQqLFrWvAXd9Vi5gu+L2KJwiSW/58tO+uX7ypszuSp4Uc6P5tdsBVldv 1QqfUKqUDZ4mK6WvDdGFUKRvUjvNrF6gqX+wjMsHBI6Kdq0JYLuwBH3GkKlpuHMD5uC6 BQ54MYnKAr0nC8g6myl8ZtFEvmud9a7t41hTPJVXWJA0J5xMZ8URu7Ncn4fmOwEka3L6 ALLQ== X-Gm-Message-State: AGRZ1gJToHzm5haCkItggfx/HlslopVNL2v7mQ4FHVj0Ga8Hh+DoxwD8 ij09CpqOlNo3ZJt4+xSy5xnH7cBVX28jPg== X-Google-Smtp-Source: AJdET5eZZyaiSrLluK0uBjnV2TOLjoyPhn7X216r4WOZ7WrFAU0GAnt1TRXL3tojPBZV+GdOMwr4Cg== X-Received: by 2002:a5d:4f08:: with SMTP id c8-v6mr5868310wru.310.1542132169833; Tue, 13 Nov 2018 10:02:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 13 Nov 2018 19:01:52 +0100 Message-Id: <20181113180154.17903-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181113180154.17903-1-richard.henderson@linaro.org> References: <20181113180154.17903-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v5 2/4] target/arm: Fill in ARMISARegisters for kvm64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 90 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 88 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 46fbe6d8ff..0a502091e7 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -456,17 +456,40 @@ static inline void unset_feature(uint64_t *features, = int feature) *features &=3D ~(1ULL << feature); } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + uint64_t ret; + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)&ret }; + int err; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + err =3D ioctl(fd, KVM_GET_ONE_REG, &idreg); + if (err < 0) { + return -1; + } + *pret =3D ret; + return 0; +} + +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. - * For AArch64 we currently don't care about ID registers at - * all; we just want to know the CPU type. */ int fdarray[3]; uint64_t features =3D 0; + int err; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. Fortunately these old kernels @@ -487,8 +510,71 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) ahcf->target =3D init.target; ahcf->dtb_compatible =3D "arm,arm-v8"; =20 + err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, + ARM64_SYS_REG(3, 0, 0, 4, 0)); + if (unlikely(err < 0)) { + /* + * Before v4.15, the kernel only exposed a limited number of system + * registers, not including any of the interesting AArch64 ID regs. + * For the most part we could leave these fields as zero with mini= mal + * effect, since this does not affect the values seen by the guest. + * + * However, it could cause problems down the line for QEMU, + * so provide a minimal v8.0 default. + * + * ??? Could read MIDR and use knowledge from cpu64.c. + * ??? Could map a page of memory into our temp guest and + * run the tiniest of hand-crafted kernels to extract + * the values seen by the guest. + * ??? Either of these sounds like too much effort just + * to work around running a modern host kernel. + */ + ahcf->isar.id_aa64pfr0 =3D 0x00000011; /* EL1&0, AArch64 only */ + err =3D 0; + } else { + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, + ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, + ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, + ARM64_SYS_REG(3, 0, 0, 6, 1)); + + /* + * Note that if AArch32 support is not present in the host, + * the AArch32 sysregs are present to be read, but will + * return UNKNOWN values. This is neither better nor worse + * than skipping the reads and leaving 0, as we must avoid + * considering the values in every case. + */ + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM64_SYS_REG(3, 0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM64_SYS_REG(3, 0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM64_SYS_REG(3, 0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM64_SYS_REG(3, 0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM64_SYS_REG(3, 0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM64_SYS_REG(3, 0, 0, 2, 7)); + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + ARM64_SYS_REG(3, 0, 0, 3, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + ARM64_SYS_REG(3, 0, 0, 3, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + ARM64_SYS_REG(3, 0, 0, 3, 2)); + } + kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 + if (err < 0) { + return false; + } + /* We can assume any KVM supporting CPU is at least a v8 * with VFPv4+Neon; this in turn implies most of the other * feature bits. --=20 2.17.2 From nobody Thu May 16 08:04:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15421331277111010.4554155537718; Tue, 13 Nov 2018 10:18:47 -0800 (PST) Received: from localhost ([::1]:55574 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMdGw-00065f-Hm for importer@patchew.org; Tue, 13 Nov 2018 13:18:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57990) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMdEC-0003Dk-VS for qemu-devel@nongnu.org; Tue, 13 Nov 2018 13:15:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMd1c-00081a-Ee for qemu-devel@nongnu.org; Tue, 13 Nov 2018 13:02:57 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:40738) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gMd1c-0007yr-6M for qemu-devel@nongnu.org; Tue, 13 Nov 2018 13:02:56 -0500 Received: by mail-wr1-x444.google.com with SMTP id p4so5186939wrt.7 for ; Tue, 13 Nov 2018 10:02:54 -0800 (PST) Received: from cloudburst.twiddle.net (26.red-176-87-105.dynamicip.rima-tde.net. [176.87.105.26]) by smtp.gmail.com with ESMTPSA id j124-v6sm2715978wmb.1.2018.11.13.10.02.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Nov 2018 10:02:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gcjpzBDmc2ewtCNL6rBuAyjW01R7ZlfO8tHcOjDumO0=; b=PO3CEbp04thuqo99BpLvgbZ5RCWbNLH2Igpi5WBSjLZWtcR130UwSu5LNVrVO88Q4K cSXqaoLVikfQ54cAqnRq1LMIW+8gp4XiVMBEfQoa4eqjCcg9jhmHyWkIlhbe7biktg4Z A6xHrUhjcClEeSCIa0Vivx4N3jGm7jzerr0EM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gcjpzBDmc2ewtCNL6rBuAyjW01R7ZlfO8tHcOjDumO0=; b=o1v+/OmbDwUA5N9CnKlcPQR49fHfKxiBNj8D0nWqTtYXwlLzBnLlT3SR2LLGbD/ZQR 3zq5MFn223s9kSrv3bEn47Hzsbh/LvwIsghgGNK8HFzA7QQUyeWERf+SpjWd+W1w5y/5 jhiMUSWiwTIJNGlr0+dDLaYibTBJ4jRljqWNa1ZHG3HakIJRffs9+tqY1pxAPBdxh5n5 kJKkUwFfNRTOseJXg/3imJzhT8xKDI4I0MpgLE0Qwf9hf1W0iEJDLOV7raH0OBDnBh+4 yqszZqlc09Cwh88YHWmGRNC9SgIdc0ER6Q8IrC7FloS25Mfm1x//o6NLnBRlaRa4fxdF 1ZAQ== X-Gm-Message-State: AGRZ1gJYOcjNqhGXab14gT4dTofteZk4xiZ7pnlTjm0sG3lBl5DpA7Gh enJ2vbIyFgEmbq79nXOxW9Q8P71im0LZmg== X-Google-Smtp-Source: AJdET5dtjlEfTVONSqfEmIoVeEcgN2wKj/oMhkF3QsEgJfoc5P2P/UYNEHaNAdnYJzlJjQyseNh2Cg== X-Received: by 2002:adf:c647:: with SMTP id u7-v6mr6070017wrg.174.1542132173197; Tue, 13 Nov 2018 10:02:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 13 Nov 2018 19:01:53 +0100 Message-Id: <20181113180154.17903-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181113180154.17903-1-richard.henderson@linaro.org> References: <20181113180154.17903-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH v5 3/4] target/arm: Introduce read_sys_reg32 for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Assert that the value to be written is the correct size. No change in functionality here, just mirroring the same function from kvm64. Signed-off-by: Richard Henderson --- target/arm/kvm32.c | 41 ++++++++++++++++------------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index cb3fb73a96..bc0badf53d 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -28,6 +28,14 @@ static inline void set_feature(uint64_t *features, int f= eature) *features |=3D 1ULL << feature; } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U32); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -35,9 +43,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. */ - int i, ret, fdarray[3]; + int err =3D 0, fdarray[3]; uint32_t midr, id_pfr0, mvfr1; uint64_t features =3D 0; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. @@ -47,23 +56,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) QEMU_KVM_ARM_TARGET_NONE }; struct kvm_vcpu_init init; - struct kvm_one_reg idregs[] =3D { - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0), - .addr =3D (uintptr_t)&midr, - }, - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0), - .addr =3D (uintptr_t)&id_pfr0, - }, - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1, - .addr =3D (uintptr_t)&mvfr1, - }, - }; =20 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { return false; @@ -77,16 +69,15 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) */ ahcf->dtb_compatible =3D "arm,arm-v7"; =20 - for (i =3D 0; i < ARRAY_SIZE(idregs); i++) { - ret =3D ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]); - if (ret) { - break; - } - } + err |=3D read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); + err |=3D read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, = 0)); + err |=3D read_sys_reg32(fdarray[2], &mvfr1, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 - if (ret) { + if (err < 0) { return false; } =20 --=20 2.17.2 From nobody Thu May 16 08:04:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542133106094282.9469513279354; Tue, 13 Nov 2018 10:18:26 -0800 (PST) Received: from localhost ([::1]:55573 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMdGb-0005Sg-28 for importer@patchew.org; Tue, 13 Nov 2018 13:18:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57899) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMdE9-0003DL-On for qemu-devel@nongnu.org; Tue, 13 Nov 2018 13:15:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMd1g-00084Z-SJ for qemu-devel@nongnu.org; Tue, 13 Nov 2018 13:03:01 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:54105) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gMd1g-00083z-Lz for qemu-devel@nongnu.org; Tue, 13 Nov 2018 13:03:00 -0500 Received: by mail-wm1-x343.google.com with SMTP id f10-v6so12869926wme.3 for ; Tue, 13 Nov 2018 10:03:00 -0800 (PST) Received: from cloudburst.twiddle.net (26.red-176-87-105.dynamicip.rima-tde.net. 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v5 4/4] target/arm: Fill in ARMISARegisters for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index bc0badf53d..bd51eb43c8 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -44,7 +44,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ah= cf) * and then query that CPU for the relevant ID registers. */ int err =3D 0, fdarray[3]; - uint32_t midr, id_pfr0, mvfr1; + uint32_t midr, id_pfr0; uint64_t features =3D 0; =20 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -71,9 +71,39 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) =20 err |=3D read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); err |=3D read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, = 0)); - err |=3D read_sys_reg32(fdarray[2], &mvfr1, + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM_CP15_REG32(0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM_CP15_REG32(0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM_CP15_REG32(0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM_CP15_REG32(0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM_CP15_REG32(0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM_CP15_REG32(0, 0, 2, 5)); + if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM_CP15_REG32(0, 0, 2, 7))) { + /* + * Older kernels don't support reading ID_ISAR6. This register was + * only introduced in ARMv8, so we can assume that it is zero on a + * CPU that a kernel this old is running on. + */ + ahcf->isar.id_isar6 =3D 0; + } + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); + /* + * FIXME: There is not yet a way to read MVFR2. + * Fortunately there is not yet anything in there that affects migrati= on. + */ =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 @@ -95,13 +125,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) if (extract32(id_pfr0, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_THUMB2EE); } - if (extract32(mvfr1, 20, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 20, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } - if (extract32(mvfr1, 12, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(mvfr1, 28, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 28, 4) =3D=3D 1) { /* FMAC support implies VFPv4 */ set_feature(&features, ARM_FEATURE_VFP4); } --=20 2.17.2