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[176.87.105.26]) by smtp.gmail.com with ESMTPSA id s16sm3479709wrt.77.2018.11.13.07.43.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Nov 2018 07:43:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CVcvIslv5WWkfBYxl9Mw9FAOSkXdpfKXat0+V0xS4Bs=; b=GqA3uVk7k+oZ4dkSt8E0OsPLnFa4USOUakEwEIu+U3j70dg0/eXEK+Ewcr7MS+MorW dZlWiYHuCqsypym/Xbw2Igh/ZU55EwczfH2VchNx1avVDqtuJZc4S80GVD5sdafPiP9X +Wp6f7KHr9qvicjjkaLjbBJZFN+y8CNy4+2AM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CVcvIslv5WWkfBYxl9Mw9FAOSkXdpfKXat0+V0xS4Bs=; b=kOEBnu80cUVRl2YA7x6Mwm8jSTtcpPHZDWd8S4zNPx5iPrHjCevBIQWH78W5RHXlGA IquEirS5aDOalll0MByUXjOtz8hgZNC3rrTuSVFmHa/DYDtOkz721Z1QQKNjxqciWkI5 +10Bw8w4vlfWsAWuFdKhgAkp2KQC/IEtsciyIuPoVx/3xHRkStRv2AZH/wmKx1nykApd h3NIETrG2nN//pOheNsIeAQOu6KlsnCsnIasiM1uCzDLPoLqS9hDwRoF5krSfQuZQQnh rAgnhBZrBQ4qry4AvReyNdac2KyGTNQ8LfDtM3WS/k9hMvu+dgaOVuVaxHUG/PE3HzKF MkLw== X-Gm-Message-State: AGRZ1gItRs/CjkFnHYz2l90r1Q0YbIeIiR4OQLE9EP8vtpX3u35yiWy7 UZMdmtBcGNXTk25TgRho81mbs5eKiV3BSg== X-Google-Smtp-Source: AJdET5ctcIgXN8FwjDpUFEjoH6kPo5JTqhs/o/s7EHVWJoGOi0DREa/EpGBKWE7m5MrEC3yCTc/80g== X-Received: by 2002:a7b:cd97:: with SMTP id y23mr2406905wmj.129.1542123801311; Tue, 13 Nov 2018 07:43:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 13 Nov 2018 16:42:26 +0100 Message-Id: <20181113154226.14396-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181113154226.14396-1-richard.henderson@linaro.org> References: <20181113154226.14396-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v4 4/4] target/arm: Fill in ARMISARegisters for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index bc0badf53d..bd51eb43c8 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -44,7 +44,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ah= cf) * and then query that CPU for the relevant ID registers. */ int err =3D 0, fdarray[3]; - uint32_t midr, id_pfr0, mvfr1; + uint32_t midr, id_pfr0; uint64_t features =3D 0; =20 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -71,9 +71,39 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) =20 err |=3D read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); err |=3D read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, = 0)); - err |=3D read_sys_reg32(fdarray[2], &mvfr1, + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM_CP15_REG32(0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM_CP15_REG32(0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM_CP15_REG32(0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM_CP15_REG32(0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM_CP15_REG32(0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM_CP15_REG32(0, 0, 2, 5)); + if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM_CP15_REG32(0, 0, 2, 7))) { + /* + * Older kernels don't support reading ID_ISAR6. This register was + * only introduced in ARMv8, so we can assume that it is zero on a + * CPU that a kernel this old is running on. + */ + ahcf->isar.id_isar6 =3D 0; + } + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); + /* + * FIXME: There is not yet a way to read MVFR2. + * Fortunately there is not yet anything in there that affects migrati= on. + */ =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 @@ -95,13 +125,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) if (extract32(id_pfr0, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_THUMB2EE); } - if (extract32(mvfr1, 20, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 20, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } - if (extract32(mvfr1, 12, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(mvfr1, 28, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 28, 4) =3D=3D 1) { /* FMAC support implies VFPv4 */ set_feature(&features, ARM_FEATURE_VFP4); } --=20 2.17.2