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[176.87.105.26]) by smtp.gmail.com with ESMTPSA id s16sm3479709wrt.77.2018.11.13.07.43.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Nov 2018 07:43:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cLRClBlTM1MdU6W5hsPIhDK5ftDIufuY11txlyX8/WA=; b=Bxm4pa+vpccCdTFuYgTLB3AdeRhUuyCNkxISb0M+E44DSqSjF6jDlMSjHhnHVmgWgR sewMX7oFy6RIZgh3fy5tKOfOZUGivAaSkAUJjgQQnWDBwmrgpDZkGcvfWfyVB+7Cu/oi 8JNtZg9v4IwLvKyl3GcqP5smNcBQsq8B1/SFA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cLRClBlTM1MdU6W5hsPIhDK5ftDIufuY11txlyX8/WA=; b=TG1OvLDQ3kdj70RcXM5PkYB96uHPhDzxfv7PsL7z6gLQcy7aXuyXQj2hp+De15AfZX MwKSTBQNMpvEgo0YL2lQwHQrG9PceJraMJSYhQFIO4etm8M7lL5pXg07cd6l4zCWJUKT lpIv3i2GRCJUgbmGCaBdvXCJeQdYx8cLHHO138ieYoht/bnlB4Gwd+A78vGYeVLJc44W LZyVrlb7D6wWWKlmV7Esbvs4ghJ/EWm0RmgytcBR9TYEET09DKc7/VWFthD9JD/LW7fC qVX/jXUZ/lEXVPu8FB3LCvjKxD07WTwFh9nxMD0A2eqiPwi4IMmvYjPmZeP/BP5Lo2jd aOWw== X-Gm-Message-State: AGRZ1gKJGWvvw3tPDxWySL74VbiPcdzvo1cqJhwvZGnZUxJ2em4KG/6Q 4wGlzHuRIilGPa8SIKncHvwBoLywn97j4g== X-Google-Smtp-Source: AJdET5ehPezZ1qdhvZc/IBJ5d7AkfP0WVLg9p+v4f/e82HIw0O46qBcTXN7QLlxZW57nF+nnluAk9Q== X-Received: by 2002:a5d:530c:: with SMTP id e12-v6mr5343995wrv.29.1542123798668; Tue, 13 Nov 2018 07:43:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 13 Nov 2018 16:42:24 +0100 Message-Id: <20181113154226.14396-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181113154226.14396-1-richard.henderson@linaro.org> References: <20181113154226.14396-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH v4 2/4] target/arm: Fill in ARMISARegisters for kvm64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 62 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 46fbe6d8ff..8dff8749c9 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -456,17 +456,40 @@ static inline void unset_feature(uint64_t *features, = int feature) *features &=3D ~(1ULL << feature); } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + uint64_t ret; + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)&ret }; + int err; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + err =3D ioctl(fd, KVM_GET_ONE_REG, &idreg); + if (err < 0) { + return -1; + } + *pret =3D ret; + return 0; +} + +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. - * For AArch64 we currently don't care about ID registers at - * all; we just want to know the CPU type. */ int fdarray[3]; uint64_t features =3D 0; + int err =3D 0; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. Fortunately these old kernels @@ -487,8 +510,43 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) ahcf->target =3D init.target; ahcf->dtb_compatible =3D "arm,arm-v8"; =20 + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM64_SYS_REG(3, 0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM64_SYS_REG(3, 0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM64_SYS_REG(3, 0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM64_SYS_REG(3, 0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM64_SYS_REG(3, 0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM64_SYS_REG(3, 0, 0, 2, 7)); + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + ARM64_SYS_REG(3, 0, 0, 3, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + ARM64_SYS_REG(3, 0, 0, 3, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + ARM64_SYS_REG(3, 0, 0, 3, 2)); + + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, + ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, + ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, + ARM64_SYS_REG(3, 0, 0, 4, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, + ARM64_SYS_REG(3, 0, 0, 4, 1)); + kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 + if (err < 0) { + return false; + } + /* We can assume any KVM supporting CPU is at least a v8 * with VFPv4+Neon; this in turn implies most of the other * feature bits. --=20 2.17.2