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[213.99.154.178]) by smtp.gmail.com with ESMTPSA id y123-v6sm3946907wme.38.2018.11.12.13.47.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 13:47:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F+bN6Efc2D8LKIXQoEGrW3N3PsuknhrH/ce++f9l7ts=; b=PJalXnPB3YAKUki1uCMEspBiyrUXkq8gyghGjIiP41rYMh8DXswoSF+0UDioRMc0ir 8wo3jUWNAToF+cXvs1AGegHCehptlsY5/aJYt33Tf6R1QhSrn4KGSqh9/F4p9XUSqI4N 0ICWQKVlmPdo9MJoaq86qg7yf+2dhEju6+uiE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F+bN6Efc2D8LKIXQoEGrW3N3PsuknhrH/ce++f9l7ts=; b=OsYK3XQFQwH2ZTjs5VPJ07sk4uSbHkCr/ATVQmu2mKYjkODaDf57Xe9Ho7KJZjlP3R 9x92OR8NpmpLCxcwX7PhPcYY5RYRc0xnyJ4k0yXWatzuODJWPubc/mCJjcn5mai0DveQ uLckXQ6xg4TWQt8SghyiK9czLUpeUNjInL28RWtcJxpTLKGXXMKFGJayr+Dw1MuOG0wj PNU4w9vcLpxNrucFJjeWzqi+fEdkW9NWO9plvFcc+424MIOq9hahadZtj2fG/bwoXMAY 5auqPe0WRHGShItxNb+Z8N5aHoT4munsoMnenQ9dIh03ZS7RJq+eDQKkTOOBRQqvMVXt ozcg== X-Gm-Message-State: AGRZ1gKvhcdYExUB/wBjE8KKVXjBeAG6Hr1BFWp1+wRv3ceiOIkp+wn5 a9mju2rlHjaFSRpMCGBKGxDDe6A06ho9Wg== X-Google-Smtp-Source: AJdET5cpBRQUGSyK3TLGTMmbF+Zoeco6xj189P1S4qdnC/N/e+EgN6veheqDLUwNTKiUUMTJzYDtHQ== X-Received: by 2002:a7b:cd87:: with SMTP id y7-v6mr1066574wmj.110.1542059230625; Mon, 12 Nov 2018 13:47:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 22:44:50 +0100 Message-Id: <20181112214503.22941-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181112214503.22941-1-richard.henderson@linaro.org> References: <20181112214503.22941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PATCH for-4.0 04/17] tcg/i386: Force qemu_ld/st arguments into fixed registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is an incremental step toward moving the qemu_ld/st code sequence out of line. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 193 +++++++++++++++++++++++++++++++------- 1 file changed, 159 insertions(+), 34 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 2a96ca4274..8a3e7690b6 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -171,6 +171,56 @@ static bool have_lzcnt; =20 static tcg_insn_unit *tb_ret_addr; =20 +#ifdef CONFIG_SOFTMMU +/* + * Constraint to choose a particular register. This is used for softmmu + * loads and stores. Registers with no assignment get an empty string. + */ +static const char * const one_reg_constraint[TCG_TARGET_NB_REGS] =3D { + [TCG_REG_EAX] =3D "a", + [TCG_REG_EBX] =3D "b", + [TCG_REG_ECX] =3D "c", + [TCG_REG_EDX] =3D "d", + [TCG_REG_ESI] =3D "S", + [TCG_REG_EDI] =3D "D", +#if TCG_TARGET_REG_BITS =3D=3D 64 + [TCG_REG_R8] =3D "E", + [TCG_REG_R9] =3D "N", +#endif +}; + +/* + * Calling convention for the softmmu load and store thunks. + * + * For 64-bit, we mostly use the host calling convention, therefore the + * real first argument is reserved for the ENV parameter that is passed + * on to the slow path helpers. + * + * For 32-bit, the host calling convention is stack based; we invent a + * private convention that uses 4 of the 6 available host registers, and + * we reserve EAX and EDX as temporaries for use by the thunk. + */ +static inline TCGReg softmmu_arg(unsigned n) +{ + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_debug_assert(n < ARRAY_SIZE(tcg_target_call_iarg_regs) - 1); + return tcg_target_call_iarg_regs[n + 1]; + } else { + static const TCGReg local_order[] =3D { + TCG_REG_ESI, TCG_REG_EDI, TCG_REG_ECX, TCG_REG_EBX + }; + tcg_debug_assert(n < ARRAY_SIZE(local_order)); + return local_order[n]; + } +} + +#define qemu_memop_arg(N) one_reg_constraint[softmmu_arg(N)] +#define qemu_memop_ret(N) (N ? "d" : "a") +#else +#define qemu_memop_arg(N) "L" +#define qemu_memop_ret(N) "L" +#endif /* CONFIG_SOFTMMU */ + static void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { @@ -1677,11 +1727,15 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, copies the entire guest address for the slow path, while truncation for the 32-bit host happens with the fastpath ADDL below. */ if (TCG_TARGET_REG_BITS =3D=3D 64) { - base =3D tcg_target_call_iarg_regs[1]; + tcg_debug_assert(addrlo =3D=3D tcg_target_call_iarg_regs[1]); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, addrlo, addrlo); + } + base =3D addrlo; } else { base =3D r1; + tcg_out_mov(s, ttype, base, addrlo); } - tcg_out_mov(s, ttype, base, addrlo); =20 /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -2006,16 +2060,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, common. */ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); + TCGReg datalo, addrlo; + TCGReg datahi __attribute__((unused)) =3D -1; + TCGReg addrhi __attribute__((unused)) =3D -1; TCGMemOpIdx oi; TCGMemOp opc; + int i =3D -1; =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi =3D *args++; + datalo =3D args[++i]; + if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { + datahi =3D args[++i]; + } + addrlo =3D args[++i]; + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + addrhi =3D args[++i]; + } + oi =3D args[++i]; opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) @@ -2024,6 +2084,15 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) tcg_insn_unit *label_ptr[2]; TCGReg base; =20 + tcg_debug_assert(datalo =3D=3D tcg_target_call_oarg_regs[0]); + if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { + tcg_debug_assert(datahi =3D=3D tcg_target_call_oarg_regs[1]); + } + tcg_debug_assert(addrlo =3D=3D softmmu_arg(0)); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_debug_assert(addrhi =3D=3D softmmu_arg(1)); + } + base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, label_ptr, offsetof(CPUTLBEntry, addr_read= )); =20 @@ -2146,16 +2215,22 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, =20 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); + TCGReg datalo, addrlo; + TCGReg datahi __attribute__((unused)) =3D -1; + TCGReg addrhi __attribute__((unused)) =3D -1; TCGMemOpIdx oi; TCGMemOp opc; + int i =3D -1; =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi =3D *args++; + datalo =3D args[++i]; + if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { + datahi =3D args[++i]; + } + addrlo =3D args[++i]; + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + addrhi =3D args[++i]; + } + oi =3D args[++i]; opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) @@ -2164,6 +2239,16 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) tcg_insn_unit *label_ptr[2]; TCGReg base; =20 + i =3D -1; + tcg_debug_assert(addrlo =3D=3D softmmu_arg(++i)); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_debug_assert(addrhi =3D=3D softmmu_arg(++i)); + } + tcg_debug_assert(datalo =3D=3D softmmu_arg(++i)); + if (TCG_TARGET_REG_BITS =3D=3D 32 && is64) { + tcg_debug_assert(datahi =3D=3D softmmu_arg(++i)); + } + base =3D tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, label_ptr, offsetof(CPUTLBEntry, addr_writ= e)); =20 @@ -2833,15 +2918,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) static const TCGTargetOpDef r_r_re =3D { .args_ct_str =3D { "r", "r", = "re" } }; static const TCGTargetOpDef r_0_re =3D { .args_ct_str =3D { "r", "0", = "re" } }; static const TCGTargetOpDef r_0_ci =3D { .args_ct_str =3D { "r", "0", = "ci" } }; - static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; - static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; - static const TCGTargetOpDef r_L_L =3D { .args_ct_str =3D { "r", "L", "= L" } }; - static const TCGTargetOpDef r_r_L =3D { .args_ct_str =3D { "r", "r", "= L" } }; - static const TCGTargetOpDef L_L_L =3D { .args_ct_str =3D { "L", "L", "= L" } }; - static const TCGTargetOpDef r_r_L_L - =3D { .args_ct_str =3D { "r", "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L_L - =3D { .args_ct_str =3D { "L", "L", "L", "L" } }; static const TCGTargetOpDef x_x =3D { .args_ct_str =3D { "x", "x" } }; static const TCGTargetOpDef x_x_x =3D { .args_ct_str =3D { "x", "x", "= x" } }; static const TCGTargetOpDef x_x_x_x @@ -3023,17 +3099,66 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) } =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_L : &r_L_L; - case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &L_L : &L_L_L; + { + static TCGTargetOpDef ld32; + ld32.args_ct_str[0] =3D qemu_memop_ret(0); + ld32.args_ct_str[1] =3D qemu_memop_arg(0); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + ld32.args_ct_str[2] =3D qemu_memop_arg(1); + } + return &ld32; + } case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &r_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L); + { + static TCGTargetOpDef ld64; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + ld64.args_ct_str[0] =3D qemu_memop_ret(0); + ld64.args_ct_str[1] =3D qemu_memop_arg(0); + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + ld64.args_ct_str[0] =3D qemu_memop_ret(0); + ld64.args_ct_str[1] =3D qemu_memop_ret(1); + ld64.args_ct_str[2] =3D qemu_memop_arg(0); + } else { + ld64.args_ct_str[0] =3D qemu_memop_ret(0); + ld64.args_ct_str[1] =3D qemu_memop_ret(1); + ld64.args_ct_str[2] =3D qemu_memop_arg(0); + ld64.args_ct_str[3] =3D qemu_memop_arg(1); + } + return &ld64; + } + + /* Recall the store value comes before addr in the opcode args + and after addr in helper args. */ + case INDEX_op_qemu_st_i32: + { + static TCGTargetOpDef st32; + st32.args_ct_str[1] =3D qemu_memop_arg(0); + if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + st32.args_ct_str[0] =3D qemu_memop_arg(1); + } else { + st32.args_ct_str[2] =3D qemu_memop_arg(1); + st32.args_ct_str[0] =3D qemu_memop_arg(2); + } + return &st32; + } case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? &L_L - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? &L_L_L - : &L_L_L_L); + { + static TCGTargetOpDef st64; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + st64.args_ct_str[1] =3D qemu_memop_arg(0); + st64.args_ct_str[0] =3D qemu_memop_arg(1); + } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + st64.args_ct_str[2] =3D qemu_memop_arg(0); + st64.args_ct_str[0] =3D qemu_memop_arg(1); + st64.args_ct_str[1] =3D qemu_memop_arg(2); + } else { + st64.args_ct_str[2] =3D qemu_memop_arg(0); + st64.args_ct_str[3] =3D qemu_memop_arg(1); + st64.args_ct_str[0] =3D qemu_memop_arg(2); + st64.args_ct_str[1] =3D qemu_memop_arg(3); + } + return &st64; + } =20 case INDEX_op_brcond2_i32: { --=20 2.17.2