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[213.99.154.178]) by smtp.gmail.com with ESMTPSA id y123-v6sm3946907wme.38.2018.11.12.13.47.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 13:47:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sXnNUWfT8Y/s5eYRqAv2JrCFIHDiypjLbLJHrnIH448=; b=AY55slyzpkJq0NNlpwAED5cGdCSfB8o3GBUbvCXE1t3NI70VOSPsNv9EwlGSaenq5c GoKH2eHIj1jPJeYCk0F+rU1IMLQxad0RpsoWmuRZr/1aGpK1rT6f72ZJp+9JrSVS6LsT aDRIqAvvORnTgFB6U9VwI6IgRqFOLWUoV+Eu4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sXnNUWfT8Y/s5eYRqAv2JrCFIHDiypjLbLJHrnIH448=; b=DdXkJMxIcl73yy7fssexqAi4pT+RwKi2RQ/2Z8KNEVdDs/2bQRzJwcB2sKZqLWioVx Idbu5Cpl+qlF7G9dhpbeSIRVOwivbmjNKIqfKlVGlQUieyCiIitmuIFphX4tq851eQse YLmY4rg4ZIoz4lHpUWdM7nhyDLgbX4Pxm1VyEp+rICXqySohZBN/BDOzWSTxxrrhrybx ci+vVbIfiYEwFcIkUtDujw1GXhLLvPm0Q2uLomBeqG/yKAalmMsDYGJpqlbENd0JBKXT HK9GjNI8eEzN/eBhFetgJ99WnthAsMPJScSamsitwIbnzjXI6w0lkqk6YNKqFvob8ksZ BI2A== X-Gm-Message-State: AGRZ1gLiq0N6EJU3OswPiQiZnTOvVIEi+JsiuZaRPLbfQtjfTDgGxRsd RdoS53HDA748voIb2P9zcFGHeCW45efqXA== X-Google-Smtp-Source: AJdET5dBg2N6XSpPX1YyyeOFBjWESoPhjkxvoRxNQCgSHWo4MF9KUy+ZoessV4S0v7vdVC5lpIAYIg== X-Received: by 2002:a1c:ee13:: with SMTP id m19-v6mr1063288wmh.142.1542059229387; Mon, 12 Nov 2018 13:47:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 22:44:49 +0100 Message-Id: <20181112214503.22941-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181112214503.22941-1-richard.henderson@linaro.org> References: <20181112214503.22941-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 03/17] tcg/i386: Change TCG_REG_L[01] to not overlap function arguments X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We will shortly be forcing qemu_ld/st arguments into registers that match the function call abi of the host, which means that the temps must be elsewhere. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 4435a7bb52..2a96ca4274 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -121,12 +121,16 @@ static const int tcg_target_call_oarg_regs[] =3D { #define TCG_CT_CONST_I32 0x400 #define TCG_CT_CONST_WSZ 0x800 =20 -/* Registers used with L constraint, which are the first argument - registers on x86_64, and two random call clobbered registers on - i386. */ +/* Registers used with L constraint, which are two random + * call clobbered registers. These should be free. + */ #if TCG_TARGET_REG_BITS =3D=3D 64 -# define TCG_REG_L0 tcg_target_call_iarg_regs[0] -# define TCG_REG_L1 tcg_target_call_iarg_regs[1] +# define TCG_REG_L0 TCG_REG_RAX +# ifdef _WIN64 +# define TCG_REG_L1 TCG_REG_R10 +# else +# define TCG_REG_L1 TCG_REG_RDI +# endif #else # define TCG_REG_L0 TCG_REG_EAX # define TCG_REG_L1 TCG_REG_EDX @@ -1625,6 +1629,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, unsigned a_mask =3D (1 << a_bits) - 1; unsigned s_mask =3D (1 << s_bits) - 1; target_ulong tlb_mask; + TCGReg base; =20 if (TCG_TARGET_REG_BITS =3D=3D 64) { if (TARGET_LONG_BITS =3D=3D 64) { @@ -1671,7 +1676,12 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg= addrlo, TCGReg addrhi, before the fastpath ADDQ below. For 64-bit guest and x32 host, MOVQ copies the entire guest address for the slow path, while truncation for the 32-bit host happens with the fastpath ADDL below. */ - tcg_out_mov(s, ttype, r1, addrlo); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + base =3D tcg_target_call_iarg_regs[1]; + } else { + base =3D r1; + } + tcg_out_mov(s, ttype, base, addrlo); =20 /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -1690,11 +1700,11 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, =20 /* TLB Hit. */ =20 - /* add addend(r0), r1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, + /* add addend(r0), base */ + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, base, r0, offsetof(CPUTLBEntry, addend) - which); =20 - return r1; + return base; } =20 /* --=20 2.17.2