From nobody Fri Dec 19 04:29:28 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542043224554332.3456465391316; Mon, 12 Nov 2018 09:20:24 -0800 (PST) Received: from localhost ([::1]:49822 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFst-0004yW-2M for importer@patchew.org; Mon, 12 Nov 2018 12:20:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMFhv-00048t-1Q for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMFhu-0000gz-99 for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:03 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52546) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gMFht-0008MG-Vh for qemu-devel@nongnu.org; Mon, 12 Nov 2018 12:09:02 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gMFhK-0005rz-Kl for qemu-devel@nongnu.org; Mon, 12 Nov 2018 17:08:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 12 Nov 2018 17:08:06 +0000 Message-Id: <20181112170816.500-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112170816.500-1-peter.maydell@linaro.org> References: <20181112170816.500-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/16] target/arm64: properly handle DBGVR RESS bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Alex Benn=C3=A9e This only fails with some (broken) versions of gdb but we should treat the top bits of DBGBVR as RESS. Properly sign extend QEMU's reference copy of dbgbvr and also update the register descriptions in the comment. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20181109152119.9242-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5de8ff0ac57..6351a54b287 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -103,7 +103,7 @@ static void kvm_arm_init_debug(CPUState *cs) * capable of fancier matching but that will require exposing that * fanciness to GDB's interface * - * D7.3.2 DBGBCR_EL1, Debug Breakpoint Control Registers + * DBGBCR_EL1, Debug Breakpoint Control Registers * * 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0 * +------+------+-------+-----+----+------+-----+------+-----+---+ @@ -115,12 +115,25 @@ static void kvm_arm_init_debug(CPUState *cs) * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12) * BAS: Byte Address Select (RES1 for AArch64) * E: Enable bit + * + * DBGBVR_EL1, Debug Breakpoint Value Registers + * + * 63 53 52 49 48 2 1 0 + * +------+-----------+----------+-----+ + * | RESS | VA[52:49] | VA[48:2] | 0 0 | + * +------+-----------+----------+-----+ + * + * Depending on the addressing mode bits the top bits of the register + * are a sign extension of the highest applicable VA bit. Some + * versions of GDB don't do it correctly so we ensure they are correct + * here so future PC comparisons will work properly. */ + static int insert_hw_breakpoint(target_ulong addr) { HWBreakpoint brk =3D { .bcr =3D 0x1, /* BCR E=3D1, enable */ - .bvr =3D addr + .bvr =3D sextract64(addr, 0, 53) }; =20 if (cur_hw_bps >=3D max_hw_bps) { --=20 2.19.1