From nobody Thu May 2 13:42:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541785110441839.4578278722381; Fri, 9 Nov 2018 09:38:30 -0800 (PST) Received: from localhost ([::1]:35335 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gLAjl-0005Rk-A9 for importer@patchew.org; Fri, 09 Nov 2018 12:38:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gLAhh-00045v-KX for qemu-devel@nongnu.org; Fri, 09 Nov 2018 12:36:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gLAhg-0001Ht-9M for qemu-devel@nongnu.org; Fri, 09 Nov 2018 12:36:21 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52472) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gLAhb-000169-Cs; Fri, 09 Nov 2018 12:36:15 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gLAhJ-0002tE-El; Fri, 09 Nov 2018 17:35:57 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 9 Nov 2018 17:35:52 +0000 Message-Id: <20181109173553.22341-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181109173553.22341-1-peter.maydell@linaro.org> References: <20181109173553.22341-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/2] target/arm: Hyp mode R14 is shared with User and System X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Adam Lackorzynski , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Hyp mode is an exception to the general rule that each AArch32 mode has its own r13, r14 and SPSR -- it has a banked r13 and SPSR but shares its r14 with User and System mode. We were incorrectly implementing it as banked, which meant that on entry to Hyp mode r14 was 0 rather than the USR/SYS r14. We provide a new function r14_bank_number() which is like the existing bank_number() but provides the index into env->banked_r14[]; bank_number() provides the index to use for env->banked_r13[] and env->banked_cpsr[]. All the points in the code that were using bank_number() to index into env->banked_r14[] are updated for consintency: * switch_mode() -- this is the only place where we fix an actual bug * aarch64_sync_32_to_64() and aarch64_sync_64_to_32(): no behavioural change as we already special-cased Hyp R14 * kvm32.c: no behavioural change since the guest can't ever be in Hyp mode, but conceptually the right thing to do * msr_banked()/mrs_banked(): we can never get to the case that accesses banked_r14[] with tgtmode =3D=3D ARM_CPU_MODE_HYP, so no behavioural change Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 16 ++++++++++++++++ target/arm/helper.c | 29 +++++++++++++++-------------- target/arm/kvm32.c | 4 ++-- target/arm/op_helper.c | 2 +- 4 files changed, 34 insertions(+), 17 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c2bb2deebd..e5341f21f6f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -145,6 +145,22 @@ static inline int bank_number(int mode) g_assert_not_reached(); } =20 +/** + * r14_bank_number: Map CPU mode onto register bank for r14 + * + * Given an AArch32 CPU mode, return the index into the saved register + * banks to use for the R14 (LR) in that mode. This is the same as + * bank_number(), except for the special case of Hyp mode, where + * R14 is shared with USR and SYS, unlike its R13 and SPSR. + * This should be used as the index into env->banked_r14[], and + * bank_number() used for the index into env->banked_r13[] and + * env->banked_spsr[]. + */ +static inline int r14_bank_number(int mode) +{ + return (mode =3D=3D ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode= ); +} + void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 96301930cc8..6fb1ddc5506 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6455,13 +6455,14 @@ static void switch_mode(CPUARMState *env, int mode) =20 i =3D bank_number(old_mode); env->banked_r13[i] =3D env->regs[13]; - env->banked_r14[i] =3D env->regs[14]; env->banked_spsr[i] =3D env->spsr; =20 i =3D bank_number(mode); env->regs[13] =3D env->banked_r13[i]; - env->regs[14] =3D env->banked_r14[i]; env->spsr =3D env->banked_spsr[i]; + + env->banked_r14[r14_bank_number(old_mode)] =3D env->regs[14]; + env->regs[14] =3D env->banked_r14[r14_bank_number(mode)]; } =20 /* Physical Interrupt Target EL Lookup Table @@ -8040,7 +8041,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) if (mode =3D=3D ARM_CPU_MODE_HYP) { env->xregs[14] =3D env->regs[14]; } else { - env->xregs[14] =3D env->banked_r14[bank_number(ARM_CPU_MODE_US= R)]; + env->xregs[14] =3D env->banked_r14[r14_bank_number(ARM_CPU_MOD= E_USR)]; } } =20 @@ -8054,7 +8055,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[16] =3D env->regs[14]; env->xregs[17] =3D env->regs[13]; } else { - env->xregs[16] =3D env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; + env->xregs[16] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_IR= Q)]; env->xregs[17] =3D env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; } =20 @@ -8062,7 +8063,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[18] =3D env->regs[14]; env->xregs[19] =3D env->regs[13]; } else { - env->xregs[18] =3D env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; + env->xregs[18] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_SV= C)]; env->xregs[19] =3D env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; } =20 @@ -8070,7 +8071,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[20] =3D env->regs[14]; env->xregs[21] =3D env->regs[13]; } else { - env->xregs[20] =3D env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; + env->xregs[20] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_AB= T)]; env->xregs[21] =3D env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; } =20 @@ -8078,7 +8079,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[22] =3D env->regs[14]; env->xregs[23] =3D env->regs[13]; } else { - env->xregs[22] =3D env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; + env->xregs[22] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_UN= D)]; env->xregs[23] =3D env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; } =20 @@ -8095,7 +8096,7 @@ void aarch64_sync_32_to_64(CPUARMState *env) env->xregs[i] =3D env->fiq_regs[i - 24]; } env->xregs[29] =3D env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; - env->xregs[30] =3D env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; + env->xregs[30] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_FI= Q)]; } =20 env->pc =3D env->regs[15]; @@ -8145,7 +8146,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) if (mode =3D=3D ARM_CPU_MODE_HYP) { env->regs[14] =3D env->xregs[14]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_USR)] =3D env->xregs[= 14]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] =3D env->xr= egs[14]; } } =20 @@ -8159,7 +8160,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] =3D env->xregs[16]; env->regs[13] =3D env->xregs[17]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[16]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[= 16]; env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[17]; } =20 @@ -8167,7 +8168,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] =3D env->xregs[18]; env->regs[13] =3D env->xregs[19]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[18]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[= 18]; env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[19]; } =20 @@ -8175,7 +8176,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] =3D env->xregs[20]; env->regs[13] =3D env->xregs[21]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[20]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[= 20]; env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[21]; } =20 @@ -8183,7 +8184,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[14] =3D env->xregs[22]; env->regs[13] =3D env->xregs[23]; } else { - env->banked_r14[bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[22]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[= 22]; env->banked_r13[bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[23]; } =20 @@ -8200,7 +8201,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->fiq_regs[i - 24] =3D env->xregs[i]; } env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[29]; - env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[30]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[= 30]; } =20 env->regs[15] =3D env->pc; diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 0f1e94c7b5e..cb3fb73a961 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -318,8 +318,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); } env->banked_r13[bn] =3D env->regs[13]; - env->banked_r14[bn] =3D env->regs[14]; env->banked_spsr[bn] =3D env->spsr; + env->banked_r14[r14_bank_number(mode)] =3D env->regs[14]; =20 /* Now we can safely copy stuff down to the kernel */ for (i =3D 0; i < ARRAY_SIZE(regs); i++) { @@ -430,8 +430,8 @@ int kvm_arch_get_registers(CPUState *cs) memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); } env->regs[13] =3D env->banked_r13[bn]; - env->regs[14] =3D env->banked_r14[bn]; env->spsr =3D env->banked_spsr[bn]; + env->regs[14] =3D env->banked_r14[r14_bank_number(mode)]; =20 /* VFP registers */ r.id =3D KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 90741f6331d..2b62c53f5b5 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -694,7 +694,7 @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t valu= e, uint32_t tgtmode, env->banked_r13[bank_number(tgtmode)] =3D value; break; case 14: - env->banked_r14[bank_number(tgtmode)] =3D value; + env->banked_r14[r14_bank_number(tgtmode)] =3D value; break; case 8 ... 12: switch (tgtmode) { --=20 2.19.1 From nobody Thu May 2 13:42:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541785420640849.9954943884188; Fri, 9 Nov 2018 09:43:40 -0800 (PST) Received: from localhost ([::1]:35364 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gLAol-000480-Jq for importer@patchew.org; Fri, 09 Nov 2018 12:43:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gLAhg-000452-Qv for qemu-devel@nongnu.org; Fri, 09 Nov 2018 12:36:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gLAhd-0001GI-IR for qemu-devel@nongnu.org; Fri, 09 Nov 2018 12:36:18 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52472) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gLAha-000169-Et; Fri, 09 Nov 2018 12:36:14 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gLAhK-0002tY-FI; Fri, 09 Nov 2018 17:35:58 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 9 Nov 2018 17:35:53 +0000 Message-Id: <20181109173553.22341-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181109173553.22341-1-peter.maydell@linaro.org> References: <20181109173553.22341-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 2/2] target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Adam Lackorzynski , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The Cortex-A15 and Cortex-A7 both have EL2; now we've implemented it properly we can enable the feature bit. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 784a4c2dfcc..b7185234d85 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1587,6 +1587,7 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A7; cpu->midr =3D 0x410fc075; @@ -1633,6 +1634,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr =3D 0x412fc0f1; --=20 2.19.1