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[2.141.114.70]) by smtp.gmail.com with ESMTPSA id l42-v6sm4411384wre.37.2018.11.08.09.54.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Nov 2018 09:54:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PpLXpocO/xsWRefCIa8us272LlmFyb71GTp1lXZH/b8=; b=PvCg1VzEBsnl23dgv1WNw0jxyaB9jwSb+cM3kIQ/BmI076aziN1pCfP+assL2l+vVP yF5Iensrm5stQgMoK6DHvs5ohcqDeLE00MEGVp+M/oZ4HUOsti1KenkIKKmNOqq95lgi YElOfgYs/8Vhjr7Lv4ElGYDfOBYc24bRXu+Dk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PpLXpocO/xsWRefCIa8us272LlmFyb71GTp1lXZH/b8=; b=fKLCtCTBZI+1/pDWZt0R38LOknqCHkMdYTfCCmmRvVNvGTdq73BRrW6ALKTJ4w3QOD sD4M2Zwh6YWRwGusQ0aWoztGua9OEsfcNGYJ4J/Ry8iBrKuV6DDnPMarBE88JDNAKIGj 3PACXbYOivqTssj75Mn44zT14mLaFwXZ5nRjlgWDhwDNZdVpFhUQ0wN4SYUf2s1CbDjV VVRrnywljoidpCS208lGO88ynItIRTJwr6Teh0sxnMgZ9tTm6eRGTDrGHuc/N071bJId tyPQMDrarBUE1mMDVhDkptEVpeLJRqC+yLgPBPXJCdSg4lW9+OGvc457D1K581ITMb45 9pvQ== X-Gm-Message-State: AGRZ1gJo4szKZBCIyKYydNUMtt0VqPft7554gnFIv27wxvlmsx0OwpaR HMQVVIwUVsptpLJ9FNInmP//yLgzisZBsQ== X-Google-Smtp-Source: AJdET5fIC2FbcfinRBKLviirU+G498ptTxZf27FHqCug+XAfzcg/5JNkNeBXIKVaoBoh9TOtlr589g== X-Received: by 2002:adf:f891:: with SMTP id u17-v6mr4991875wrp.178.1541699689959; Thu, 08 Nov 2018 09:54:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Nov 2018 18:52:42 +0100 Message-Id: <20181108175246.13416-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181108175246.13416-1-richard.henderson@linaro.org> References: <20181108175246.13416-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v3 1/5] target/arm: Install ARMISARegisters from kvm host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ID registers are replacing (some of) the feature bits. We need (some of) these values to determine the set of data to be handled during migration. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/kvm_arm.h | 1 + target/arm/kvm.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 21c0129da2..6393455b1d 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -183,6 +183,7 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); * by asking the host kernel) */ typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; uint64_t features; uint32_t target; const char *dtb_compatible; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 09a86e2820..44dd0ce6ce 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -158,6 +158,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) =20 cpu->kvm_target =3D arm_host_cpu_features.target; cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; + cpu->isar =3D arm_host_cpu_features.isar; env->features =3D arm_host_cpu_features.features; } =20 --=20 2.17.2 From nobody Mon Apr 29 12:36:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541700103173750.7824234317558; Thu, 8 Nov 2018 10:01:43 -0800 (PST) Received: from localhost ([::1]:58374 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKocg-00085T-5N for importer@patchew.org; Thu, 08 Nov 2018 13:01:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKoW8-0001c7-Dg for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKoW4-0008AR-PY for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:56 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:40272) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gKoW4-00089z-Il for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:52 -0500 Received: by mail-wr1-x441.google.com with SMTP id i17-v6so22220236wre.7 for ; Thu, 08 Nov 2018 09:54:52 -0800 (PST) Received: from cloudburst.twiddle.net (70.red-2-141-114.dynamicip.rima-tde.net. [2.141.114.70]) by smtp.gmail.com with ESMTPSA id l42-v6sm4411384wre.37.2018.11.08.09.54.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Nov 2018 09:54:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6uQuU327VC/BRal1lZ+nVzurXjaVdMxrSfBdC83uyXQ=; b=AdXeHyjb4bhTngj2jOmlKAc+dTMxjLHweNLh6SHBSnPE0K3GeEmT3U3xirg7jyd1e/ 9umS4anC7dFpYyxGLE2d4zVVd+OS/aj2jO//ZoznjvfVngGp2SyF9ux/HAxeZ4DZXxBo DDOyDu+DmeJplsM5Wuhk/URBVkdQMAhYMXx6k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6uQuU327VC/BRal1lZ+nVzurXjaVdMxrSfBdC83uyXQ=; b=qYLY/WeiFlAyrhPG8/24BXjXeyRjd0GrlbuBu3i/94UismyNRZoael7qc7Of4AxoAq j8Xe/7akM0wN5Nll+UZ++q35ODcP4T0YZEXL9bR5lmOfZEFTM7p5zykshbQzZFozpn5t xn5hsCP74Pj6VAOgzjPrs+hu2wjsmAotnQKWD6sSN5/JfRaZeqiL8SY6PDAcHZIVH1vU MsqOIBqjNAqoMaVwdOrTWN/JW9MYDDMJ35smLNDYn27VOo1VOiOyNaIcsAjLZkl3nmLj BwPWdVMoLF2zYHmDoUWdTCdg9LSC8AlRZs1LkicDd/TPRGE8inKwH7bkNepfVqnJjUO1 nhKQ== X-Gm-Message-State: AGRZ1gJTnfqE6vQCgOldzk3Ny+BzrPyNa+em6qlu+I3S74YAMCs26d8v PxBKD0Qv7kMxiyeOwyYcuXaGsS0JLYeHRg== X-Google-Smtp-Source: AJdET5cAWagJxvOeHXx7mowjecu1iC1Gam2xbY7wzOi7kY8VI5ZyvBfvfHExjW8J0BjmXZGn3qU8NA== X-Received: by 2002:adf:fb12:: with SMTP id c18-v6mr5172342wrr.200.1541699691212; Thu, 08 Nov 2018 09:54:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Nov 2018 18:52:43 +0100 Message-Id: <20181108175246.13416-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181108175246.13416-1-richard.henderson@linaro.org> References: <20181108175246.13416-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v3 2/5] target/arm: Fill in ARMISARegisters for kvm64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 90 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 88 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5de8ff0ac5..e1128b94b2 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -443,17 +443,40 @@ static inline void unset_feature(uint64_t *features, = int feature) *features &=3D ~(1ULL << feature); } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + uint64_t ret; + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)&ret }; + int err; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + err =3D ioctl(fd, KVM_GET_ONE_REG, &idreg); + if (err < 0) { + return -1; + } + *pret =3D ret; + return 0; +} + +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. - * For AArch64 we currently don't care about ID registers at - * all; we just want to know the CPU type. */ int fdarray[3]; uint64_t features =3D 0; + int err; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. Fortunately these old kernels @@ -474,8 +497,71 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) ahcf->target =3D init.target; ahcf->dtb_compatible =3D "arm,arm-v8"; =20 + err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, + ARM64_SYS_REG(3, 0, 0, 4, 0)); + if (unlikely(err < 0)) { + /* + * Before v4.15, the kernel only exposed a limited number of system + * registers, not including any of the interesting AArch64 ID regs. + * For the most part we could leave these fields as zero with mini= mal + * effect, since this does not affect the values seen by the guest. + * + * However, it could cause problems down the line for QEMU, + * so provide a minimal v8.0 default. + * + * ??? Could read MIDR and use knowledge from cpu64.c. + * ??? Could map a page of memory into our temp guest and + * run the tiniest of hand-crafted kernels to extract + * the values seen by the guest. + * ??? Either of these sounds like too much effort just + * to work around running a modern host kernel. + */ + ahcf->isar.id_aa64pfr0 =3D 0x00000011; /* EL1&0, AArch64 only */ + err =3D 0; + } else { + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, + ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, + ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, + ARM64_SYS_REG(3, 0, 0, 6, 1)); + + /* + * Note that if AArch32 support is not present in the host, + * the AArch32 sysregs are present to be read, but will + * return UNKNOWN values. This is neither better nor worse + * than skipping the reads and leaving 0, as we must avoid + * considering the values in every case. + */ + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM64_SYS_REG(3, 0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM64_SYS_REG(3, 0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM64_SYS_REG(3, 0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM64_SYS_REG(3, 0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM64_SYS_REG(3, 0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM64_SYS_REG(3, 0, 0, 2, 7)); + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + ARM64_SYS_REG(3, 0, 0, 3, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + ARM64_SYS_REG(3, 0, 0, 3, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + ARM64_SYS_REG(3, 0, 0, 3, 2)); + } + kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 + if (err < 0) { + return false; + } + /* We can assume any KVM supporting CPU is at least a v8 * with VFPv4+Neon; this in turn implies most of the other * feature bits. --=20 2.17.2 From nobody Mon Apr 29 12:36:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541699977982979.2864188868058; Thu, 8 Nov 2018 09:59:37 -0800 (PST) Received: from localhost ([::1]:58356 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKoae-0005pv-MY for importer@patchew.org; Thu, 08 Nov 2018 12:59:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39536) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKoW8-0001cB-E5 for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKoW5-0008BA-OH for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:56 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:34814) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gKoW5-0008Af-IQ for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:53 -0500 Received: by mail-wr1-x443.google.com with SMTP id j26-v6so22245573wre.1 for ; Thu, 08 Nov 2018 09:54:53 -0800 (PST) Received: from cloudburst.twiddle.net (70.red-2-141-114.dynamicip.rima-tde.net. [2.141.114.70]) by smtp.gmail.com with ESMTPSA id l42-v6sm4411384wre.37.2018.11.08.09.54.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Nov 2018 09:54:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wAAqQsydo91GFkx0Iu9I74oQUpqdHqV7ni9QirCbmpY=; b=gQXEy2uN88J7Yo7w6NMfD53nZ+4U4HgzHJHSj/vAzj4EMwvD4FHsPQsy4oDvuDNnME jwsxUVwr9SVB6OCbLYj/KJxHF4GLdbpMU/72zYvdvILx8JfhglJsmlyr/nWcYFDvfT28 fgipWiKTnRibtBFmAELV5qjvXRyqtqk4PLysA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wAAqQsydo91GFkx0Iu9I74oQUpqdHqV7ni9QirCbmpY=; b=p4bKMhUFfWQ2BlO7Ch886Ks0siU59cZnvQu1nHRwKhqyVWAevKK6OhSBK7kTvyu+vd sFzszC99Ye+YHtPnq/YKdrizN3g5C20smZklxpY2vWJ4JmOUsIFSRfRGuwjYT1q9Y5EU CxiAoRWgHeyPZVtHKhkm4Jqg3iLaASUM0QY3ktT4Fz3o+6BXHOH3eyJJ1YXtEPsLJU5W Hfh4kYXFDRFYlr86s26+YVLS2/bbrcIGC1W92UReJEB3SFWasaSGjAAN0LJ5LcA11SFN NbgFLRAO946AUySiynHxLyI3CmX1qPqsWRfzrpEsBaGiRzxw8dy0XOsrmzqUM+2RdJbN JTow== X-Gm-Message-State: AGRZ1gKW57ZtxanKeCWDYgKF2OHygz0Cb8/NM7YyOINhIJq0ihsGHIK5 gRUK5pyX+8vDCAjhjjFoV6nDUEN5lftkpA== X-Google-Smtp-Source: AJdET5ckb81AkPhDtdkYMyD6oNLw6poga8iefUZ79UYOKzyS3B97jIlFYYiCmzBYav5DCYW2D7amFg== X-Received: by 2002:a5d:4708:: with SMTP id y8-v6mr5438396wrq.16.1541699692309; Thu, 08 Nov 2018 09:54:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Nov 2018 18:52:44 +0100 Message-Id: <20181108175246.13416-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181108175246.13416-1-richard.henderson@linaro.org> References: <20181108175246.13416-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v3 3/5] target/arm: Introduce read_sys_reg32 for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Assert that the value to be written is the correct size. No change in functionality here, just mirroring the same function from kvm64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/kvm32.c | 41 ++++++++++++++++------------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 0f1e94c7b5..de573f9aa8 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -28,6 +28,14 @@ static inline void set_feature(uint64_t *features, int f= eature) *features |=3D 1ULL << feature; } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U32); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -35,9 +43,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. */ - int i, ret, fdarray[3]; + int err =3D 0, fdarray[3]; uint32_t midr, id_pfr0, mvfr1; uint64_t features =3D 0; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. @@ -47,23 +56,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) QEMU_KVM_ARM_TARGET_NONE }; struct kvm_vcpu_init init; - struct kvm_one_reg idregs[] =3D { - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0), - .addr =3D (uintptr_t)&midr, - }, - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0), - .addr =3D (uintptr_t)&id_pfr0, - }, - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1, - .addr =3D (uintptr_t)&mvfr1, - }, - }; =20 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { return false; @@ -77,16 +69,15 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) */ ahcf->dtb_compatible =3D "arm,arm-v7"; =20 - for (i =3D 0; i < ARRAY_SIZE(idregs); i++) { - ret =3D ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]); - if (ret) { - break; - } - } + err |=3D read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); + err |=3D read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, = 0)); + err |=3D read_sys_reg32(fdarray[2], &mvfr1, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 - if (ret) { + if (err < 0) { return false; } =20 --=20 2.17.2 From nobody Mon Apr 29 12:36:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541699808852371.1317575949614; Thu, 8 Nov 2018 09:56:48 -0800 (PST) Received: from localhost ([::1]:58339 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKoXr-0002ao-V1 for importer@patchew.org; Thu, 08 Nov 2018 12:56:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39545) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKoW8-0001cD-JM for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKoW7-0008Cl-EG for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:56 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:36225) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gKoW7-0008Bw-6R for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:55 -0500 Received: by mail-wr1-x444.google.com with SMTP id z13-v6so19844123wrs.3 for ; Thu, 08 Nov 2018 09:54:54 -0800 (PST) Received: from cloudburst.twiddle.net (70.red-2-141-114.dynamicip.rima-tde.net. [2.141.114.70]) by smtp.gmail.com with ESMTPSA id l42-v6sm4411384wre.37.2018.11.08.09.54.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Nov 2018 09:54:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Xb8qasGGEBVJuzUJvReZfnwfw3l/sa7Djl2gXpUSNbI=; b=Kbxa93T5t7ZLwlFtc6CCj6X9YXueMS0TjwI435j0TefkO1bNI4Pky9czNZ2PmgF/z5 1xei0ZWuPWlc+2Fs9Z0PIQ0ueF7JPp6rfLplUwmNMGMNyD49kkGzqCKqJgG8kS6LLN7u aDqkeX1j/0dhI51AzjBoawlKmzksB48rusWF8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Xb8qasGGEBVJuzUJvReZfnwfw3l/sa7Djl2gXpUSNbI=; b=gBtyI/ESK3zx+GkrOYZxhPIG4zMZu/STklikp1BlfxLI1Sr1iGbmVe2PXFSxJ4VmSa qDmtH++e3TO28VivJ28O3BsuSxB/NgRzMoL45PsZ3IcQIVv4TNo1oX8YqTMhaxz6OGGR PdAEy5NoTnE9ubDQtjp0o5hcxPKp7cIt9cszJRGUiEArkCcQtT3G8GuaxVpmOa6MtfQq 4j3gFrz/4w4DD3pqmXn+hf94for8VV6Qrh7ZyI1fYvcB8G+qk8rxBB0rE6HbfHIrqUPl Icu4mlEMaj6OtuV80S44DTcUVWOvljrzNFqWobMiD+C5P6R4el398nEms+GBLpCR8zPd Ly0w== X-Gm-Message-State: AGRZ1gK1077iZ5n6tq/Ybn6GMez/PaUIPTVJ7YJyYzKK1HvZTLTl9WiU +rn37oDKai8jfViT8AuNqOsXTMa0HHhv1Q== X-Google-Smtp-Source: AJdET5dnu3wryjWMaCI5aIkstSPa0DWPT3VO5tJg5dTFYP4lIv5zcm2UzsPcOrfpbfo8f69JNjNS7w== X-Received: by 2002:adf:9441:: with SMTP id 59-v6mr4860421wrq.305.1541699693655; Thu, 08 Nov 2018 09:54:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Nov 2018 18:52:45 +0100 Message-Id: <20181108175246.13416-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181108175246.13416-1-richard.henderson@linaro.org> References: <20181108175246.13416-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH v3 4/5] target/arm: Fill in ARMISARegisters for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/kvm32.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index de573f9aa8..9ededa3c73 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -44,7 +44,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ah= cf) * and then query that CPU for the relevant ID registers. */ int err =3D 0, fdarray[3]; - uint32_t midr, id_pfr0, mvfr1; + uint32_t midr, id_pfr0; uint64_t features =3D 0; =20 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -71,9 +71,32 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) =20 err |=3D read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); err |=3D read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, = 0)); - err |=3D read_sys_reg32(fdarray[2], &mvfr1, + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM_CP15_REG32(0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM_CP15_REG32(0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM_CP15_REG32(0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM_CP15_REG32(0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM_CP15_REG32(0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM_CP15_REG32(0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM_CP15_REG32(0, 0, 2, 7)); + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); + /* + * FIXME: There is not yet a way to read MVFR2. + * Fortunately there is not yet anything in there that affects migrati= on. + */ =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 @@ -95,13 +118,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) if (extract32(id_pfr0, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_THUMB2EE); } - if (extract32(mvfr1, 20, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 20, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } - if (extract32(mvfr1, 12, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(mvfr1, 28, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 28, 4) =3D=3D 1) { /* FMAC support implies VFPv4 */ set_feature(&features, ARM_FEATURE_VFP4); } --=20 2.17.2 From nobody Mon Apr 29 12:36:39 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541700190100902.027513785912; Thu, 8 Nov 2018 10:03:10 -0800 (PST) Received: from localhost ([::1]:58379 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKoe5-0000ug-3E for importer@patchew.org; Thu, 08 Nov 2018 13:03:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39614) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKoWB-0001d7-Aa for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:55:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKoW8-0008Ek-MN for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:59 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:38475) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gKoW8-0008Cv-8q for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:56 -0500 Received: by mail-wm1-x344.google.com with SMTP id f2-v6so2033299wme.3 for ; Thu, 08 Nov 2018 09:54:56 -0800 (PST) Received: from cloudburst.twiddle.net (70.red-2-141-114.dynamicip.rima-tde.net. [2.141.114.70]) by smtp.gmail.com with ESMTPSA id l42-v6sm4411384wre.37.2018.11.08.09.54.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Nov 2018 09:54:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zlFdkBkZo5nt5LFadOS5kmImPmiLZuKCuNQcIkYLDuU=; b=iKmxGaMW4tihGC/qQdP4MkkPVOeTV3lkT+LEx6VeHFTUeNlVXS821ei5djZx+OAh9X GGMv2/6LEyFZiAa/xrwwD2/C0bKBvMmJcNIIfMITE/frD1lrZL2TPw1ha5uMubU/ZJd3 syD7pbaYkRKxkP2j8fs55pyrTBEhuvxNOsAoE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zlFdkBkZo5nt5LFadOS5kmImPmiLZuKCuNQcIkYLDuU=; b=JVwasmVQXejaxaANU1XxwGZAuJIthsEC5AbR8bWY+x1xLgEXo89UQAVPR/nfOkH9F8 KtYmuh856jwNsY6ZOzRwaY/jeCBVJRqSbC1VatfpjB1R4hUeaM/cQrIu5mexJjQx5VZU MyUJTsivH9UqgtsDDmvZiacxiAM0z3SFbxIXoTZRuL81/RKf2fOG7j3R0nwLw00Ps+ja JsU1vAQ16O70BFPCjhoKY3CdWMiKY93fIkzOnAyjryMF2Y9yGpdu3BW7SZGk7Ufgey21 TQDkgqa0Ca6Re95kgOlc5ZNCu6bEJFPYIWobXXpbwaGaYLoURo6mnJm4IvmG666lLyQH ev0w== X-Gm-Message-State: AGRZ1gLVHrqW1DPAReEIgoIORpYtDeHMGQXkhBHYCv1uzcFucggymQ2T ShBmo4bQOu45rgAwFcB8dr5RCINwGcTXDA== X-Google-Smtp-Source: AJdET5fOICvxwJ4Tszzwfwt89At0o7D2KkCiQ2V1m6OwKTRDMLTuj1F3DuKFAOkioKtefTgnI38W+w== X-Received: by 2002:a1c:5885:: with SMTP id m127-v6mr2005469wmb.118.1541699694705; Thu, 08 Nov 2018 09:54:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Nov 2018 18:52:46 +0100 Message-Id: <20181108175246.13416-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181108175246.13416-1-richard.henderson@linaro.org> References: <20181108175246.13416-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v3 5/5] target/arm: Convert t32ee from feature bit to isar3 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 6 +++++- linux-user/elfload.c | 2 +- target/arm/cpu.c | 4 ---- target/arm/helper.c | 2 +- target/arm/kvm32.c | 3 --- target/arm/machine.c | 3 +-- 6 files changed, 8 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b5eff79f73..5c2c77c31d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1575,7 +1575,6 @@ enum arm_features { ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE, ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ ARM_FEATURE_V4T, @@ -3172,6 +3171,11 @@ static inline bool isar_feature_jazelle(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; } =20 +static inline bool isar_feature_t32ee(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar3, ID_ISAR3, T32EE) !=3D 0; +} + static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) !=3D 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5bccd2e243..a3503c83c9 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -466,7 +466,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); - GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + GET_FEATURE_ID(t32ee, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 784a4c2dfc..d4dc0bc225 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1451,7 +1451,6 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr =3D 0x410fc080; @@ -1520,7 +1519,6 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different @@ -1583,7 +1581,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); @@ -1629,7 +1626,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); diff --git a/target/arm/helper.c b/target/arm/helper.c index 96301930cc..e28770833a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5457,7 +5457,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + if (cpu_isar_feature(t32ee, cpu)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 9ededa3c73..8b2c9b3075 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -115,9 +115,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) set_feature(&features, ARM_FEATURE_VFP3); set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 - if (extract32(id_pfr0, 12, 4) =3D=3D 1) { - set_feature(&features, ARM_FEATURE_THUMB2EE); - } if (extract32(ahcf->isar.mvfr1, 20, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } diff --git a/target/arm/machine.c b/target/arm/machine.c index 239fe4e84d..07f904709a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -321,9 +321,8 @@ static const VMStateDescription vmstate_m =3D { static bool thumb2ee_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_THUMB2EE); + return cpu_isar_feature(t32ee, cpu); } =20 static const VMStateDescription vmstate_thumb2ee =3D { --=20 2.17.2