From nobody Thu Nov 6 14:31:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154144189354523.255300288985154; Mon, 5 Nov 2018 10:18:13 -0800 (PST) Received: from localhost ([::1]:36875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJjS0-00007l-CD for importer@patchew.org; Mon, 05 Nov 2018 13:18:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJjPf-00073w-Iy for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:15:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJjPZ-0001vc-Ce for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:15:43 -0500 Received: from mx1.redhat.com ([209.132.183.28]:34026) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gJjPY-0001sv-Vh for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:15:41 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F1843A4053; Mon, 5 Nov 2018 18:15:36 +0000 (UTC) Received: from redhat.com (ovpn-121-251.rdu2.redhat.com [10.10.121.251]) by smtp.corp.redhat.com (Postfix) with SMTP id EFB3B6013B; Mon, 5 Nov 2018 18:15:35 +0000 (UTC) Date: Mon, 5 Nov 2018 13:15:35 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <20181105181353.39804-7-mst@redhat.com> References: <20181105181353.39804-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20181105181353.39804-1-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Mon, 05 Nov 2018 18:15:37 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 06/33] intel_iommu: introduce vtd_reset_caches() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Jason Wang , Peter Xu , Eric Auger , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Peter Xu Provide the function and use it in vtd_init(). Used to reset both context entry cache and iotlb cache for the whole IOMMU unit. Signed-off-by: Peter Xu Reviewed-by: Eric Auger Reviewed-by: Jason Wang Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/intel_iommu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3dfada19a6..1137861a9d 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -227,6 +227,14 @@ static void vtd_reset_iotlb(IntelIOMMUState *s) vtd_iommu_unlock(s); } =20 +static void vtd_reset_caches(IntelIOMMUState *s) +{ + vtd_iommu_lock(s); + vtd_reset_iotlb_locked(s); + vtd_reset_context_cache_locked(s); + vtd_iommu_unlock(s); +} + static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id, uint32_t level) { @@ -3160,10 +3168,7 @@ static void vtd_init(IntelIOMMUState *s) s->cap |=3D VTD_CAP_CM; } =20 - vtd_iommu_lock(s); - vtd_reset_context_cache_locked(s); - vtd_reset_iotlb_locked(s); - vtd_iommu_unlock(s); + vtd_reset_caches(s); =20 /* Define registers with default values and bit semantics */ vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0); --=20 MST