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Tsirkin" To: qemu-devel@nongnu.org Message-ID: <20181105181353.39804-19-mst@redhat.com> References: <20181105181353.39804-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20181105181353.39804-1-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Mon, 05 Nov 2018 18:16:40 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 18/33] x86_iommu/amd: Add interrupt remap support when VAPIC is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "Singh, Brijesh" , Eduardo Habkost , Tom Lendacky , Peter Xu , Paolo Bonzini , Suravee Suthikulpanit , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Singh, Brijesh" Emulate the interrupt remapping support when guest virtual APIC is enabled. For more information refer: IOMMU spec rev 3.0 (section 2.2.5.2) When VAPIC is enabled, it uses interrupt remapping as defined in Table 22 and Figure 17 from IOMMU spec. Signed-off-by: Brijesh Singh Reviewed-by: Peter Xu Cc: Peter Xu Cc: "Michael S. Tsirkin" Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Cc: Marcel Apfelbaum Cc: Tom Lendacky Cc: Suravee Suthikulpanit Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/amd_iommu.h | 36 +++++++++++++++++++++++ hw/i386/amd_iommu.c | 69 +++++++++++++++++++++++++++++++++++++++++++- hw/i386/trace-events | 2 ++ 3 files changed, 106 insertions(+), 1 deletion(-) diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index f73be48fca..8061e9c49c 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -103,6 +103,7 @@ #define AMDVI_MMIO_CONTROL_EVENTINTEN (1ULL << 3) #define AMDVI_MMIO_CONTROL_COMWAITINTEN (1ULL << 4) #define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12) +#define AMDVI_MMIO_CONTROL_GAEN (1ULL << 17) =20 /* MMIO status register bits */ #define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) @@ -263,6 +264,38 @@ union irte { } fields; }; =20 +/* Interrupt remapping table fields (Guest VAPIC is enabled) */ +union irte_ga_lo { + uint64_t val; + + /* For int remapping */ + struct { + uint64_t valid:1, + no_fault:1, + /* ------ */ + int_type:3, + rq_eoi:1, + dm:1, + /* ------ */ + guest_mode:1, + destination:8, + rsvd_1:48; + } fields_remap; +}; + +union irte_ga_hi { + uint64_t val; + struct { + uint64_t vector:8, + rsvd_2:56; + } fields; +}; + +struct irte_ga { + union irte_ga_lo lo; + union irte_ga_hi hi; +}; + #define TYPE_AMD_IOMMU_DEVICE "amd-iommu" #define AMD_IOMMU_DEVICE(obj)\ OBJECT_CHECK(AMDVIState, (obj), TYPE_AMD_IOMMU_DEVICE) @@ -332,6 +365,9 @@ typedef struct AMDVIState { =20 /* IOTLB */ GHashTable *iotlb; + + /* Interrupt remapping */ + bool ga_enabled; } AMDVIState; =20 #endif diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 8e2f13c029..353a810e6b 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -608,6 +608,7 @@ static void amdvi_handle_control_write(AMDVIState *s) s->completion_wait_intr =3D !!(control & AMDVI_MMIO_CONTROL_COMWAITINT= EN); s->cmdbuf_enabled =3D s->enabled && !!(control & AMDVI_MMIO_CONTROL_CMDBUFLEN); + s->ga_enabled =3D !!(control & AMDVI_MMIO_CONTROL_GAEN); =20 /* update the flags depending on the control register */ if (s->cmdbuf_enabled) { @@ -1094,6 +1095,65 @@ static int amdvi_int_remap_legacy(AMDVIState *iommu, return 0; } =20 +static int amdvi_get_irte_ga(AMDVIState *s, MSIMessage *origin, uint64_t *= dte, + struct irte_ga *irte, uint16_t devid) +{ + uint64_t irte_root, offset; + + irte_root =3D dte[2] & AMDVI_IR_PHYS_ADDR_MASK; + offset =3D (origin->data & AMDVI_IRTE_OFFSET) << 4; + trace_amdvi_ir_irte(irte_root, offset); + + if (dma_memory_read(&address_space_memory, irte_root + offset, + irte, sizeof(*irte))) { + trace_amdvi_ir_err("failed to get irte_ga"); + return -AMDVI_IR_GET_IRTE; + } + + trace_amdvi_ir_irte_ga_val(irte->hi.val, irte->lo.val); + return 0; +} + +static int amdvi_int_remap_ga(AMDVIState *iommu, + MSIMessage *origin, + MSIMessage *translated, + uint64_t *dte, + X86IOMMUIrq *irq, + uint16_t sid) +{ + int ret; + struct irte_ga irte; + + /* get interrupt remapping table */ + ret =3D amdvi_get_irte_ga(iommu, origin, dte, &irte, sid); + if (ret < 0) { + return ret; + } + + if (!irte.lo.fields_remap.valid) { + trace_amdvi_ir_target_abort("RemapEn is disabled"); + return -AMDVI_IR_TARGET_ABORT; + } + + if (irte.lo.fields_remap.guest_mode) { + error_report_once("guest mode is not zero"); + return -AMDVI_IR_ERR; + } + + if (irte.lo.fields_remap.int_type > AMDVI_IOAPIC_INT_TYPE_ARBITRATED) { + error_report_once("reserved int_type is set"); + return -AMDVI_IR_ERR; + } + + irq->delivery_mode =3D irte.lo.fields_remap.int_type; + irq->vector =3D irte.hi.fields.vector; + irq->dest_mode =3D irte.lo.fields_remap.dm; + irq->redir_hint =3D irte.lo.fields_remap.rq_eoi; + irq->dest =3D irte.lo.fields_remap.destination; + + return 0; +} + static int __amdvi_int_remap_msi(AMDVIState *iommu, MSIMessage *origin, MSIMessage *translated, @@ -1101,6 +1161,7 @@ static int __amdvi_int_remap_msi(AMDVIState *iommu, X86IOMMUIrq *irq, uint16_t sid) { + int ret; uint8_t int_ctl; =20 int_ctl =3D (dte[2] >> AMDVI_IR_INTCTL_SHIFT) & 3; @@ -1120,7 +1181,13 @@ static int __amdvi_int_remap_msi(AMDVIState *iommu, return -AMDVI_IR_ERR; } =20 - return amdvi_int_remap_legacy(iommu, origin, translated, dte, irq, sid= ); + if (iommu->ga_enabled) { + ret =3D amdvi_int_remap_ga(iommu, origin, translated, dte, irq, si= d); + } else { + ret =3D amdvi_int_remap_legacy(iommu, origin, translated, dte, irq= , sid); + } + + return ret; } =20 /* Interrupt remapping for MSI/MSI-X entry */ diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 98150c93db..6ac347d18c 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -113,6 +113,8 @@ amdvi_ir_intctl(uint8_t val) "int_ctl 0x%"PRIx8 amdvi_ir_target_abort(const char *str) "%s" amdvi_ir_delivery_mode(const char *str) "%s" amdvi_ir_generate_msi_message(uint8_t vector, uint8_t delivery_mode, uint8= _t dest_mode, uint8_t dest, uint8_t rh) "vector %d delivery-mode %d dest-mo= de %d dest-id %d rh %d" +amdvi_ir_irte_ga(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" offset 0x= %"PRIx64 +amdvi_ir_irte_ga_val(uint64_t hi, uint64_t lo) "hi 0x%"PRIx64" lo 0x%"PRIx= 64 =20 # hw/i386/vmport.c vmport_register(unsigned char command, void *func, void *opaque) "command:= 0x%02x func: %p opaque: %p" --=20 MST