From nobody Thu Nov 6 14:35:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541442966851213.79208953315197; Mon, 5 Nov 2018 10:36:06 -0800 (PST) Received: from localhost ([::1]:36983 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJjjF-0003kQ-Qp for importer@patchew.org; Mon, 05 Nov 2018 13:36:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60459) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJjQf-0007sW-C4 for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:16:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJjQc-00034y-Qb for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:16:49 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42824) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gJjQc-0002rl-FE for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:16:46 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5EA5A8F4EB; Mon, 5 Nov 2018 18:16:29 +0000 (UTC) Received: from redhat.com (ovpn-121-251.rdu2.redhat.com [10.10.121.251]) by smtp.corp.redhat.com (Postfix) with SMTP id D764A1054FDA; Mon, 5 Nov 2018 18:16:27 +0000 (UTC) Date: Mon, 5 Nov 2018 13:16:27 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <20181105181353.39804-14-mst@redhat.com> References: <20181105181353.39804-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20181105181353.39804-1-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Mon, 05 Nov 2018 18:16:29 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 13/33] x86_iommu/amd: remove V=1 check from amdvi_validate_dte() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "Singh, Brijesh" , Eduardo Habkost , Tom Lendacky , Peter Xu , Paolo Bonzini , Suravee Suthikulpanit , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Singh, Brijesh" Currently, the amdvi_validate_dte() assumes that a valid DTE will always have V=3D1. This is not true. The V=3D1 means that bit[127:1] are valid. A valid DTE can have IV=3D1 and V=3D0 (i.e address translation disabled and interrupt remapping enabled) Remove the V=3D1 check from amdvi_validate_dte(), make the caller responsible to check for V or IV bits. This also fixes a bug in existing code that when error is detected during the translation we'll fail the translation instead of assuming a passthrough mode. Signed-off-by: Brijesh Singh Reviewed-by: Peter Xu Cc: Peter Xu Cc: "Michael S. Tsirkin" Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Cc: Marcel Apfelbaum Cc: Tom Lendacky Cc: Suravee Suthikulpanit Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/amd_iommu.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 1fd669fef8..7206bb09c2 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -807,7 +807,7 @@ static inline uint64_t amdvi_get_perms(uint64_t entry) AMDVI_DEV_PERM_SHIFT; } =20 -/* a valid entry should have V =3D 1 and reserved bits honoured */ +/* validate that reserved bits are honoured */ static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid, uint64_t *dte) { @@ -820,7 +820,7 @@ static bool amdvi_validate_dte(AMDVIState *s, uint16_t = devid, return false; } =20 - return dte[0] & AMDVI_DEV_VALID; + return true; } =20 /* get a device table entry given the devid */ @@ -966,8 +966,12 @@ static void amdvi_do_translate(AMDVIAddressSpace *as, = hwaddr addr, return; } =20 - /* devices with V =3D 0 are not translated */ if (!amdvi_get_dte(s, devid, entry)) { + return; + } + + /* devices with V =3D 0 are not translated */ + if (!(entry[0] & AMDVI_DEV_VALID)) { goto out; } =20 --=20 MST