From nobody Thu Nov 6 14:34:06 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541442557565379.545700793367; Mon, 5 Nov 2018 10:29:17 -0800 (PST) Received: from localhost ([::1]:36946 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJjci-00055I-DK for importer@patchew.org; Mon, 05 Nov 2018 13:29:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60490) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJjQg-0007t9-1q for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:16:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJjQd-00035t-6q for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:16:49 -0500 Received: from mx1.redhat.com ([209.132.183.28]:49321) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gJjQc-0002r4-NK for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:16:47 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6229930014A2; Mon, 5 Nov 2018 18:16:27 +0000 (UTC) Received: from redhat.com (ovpn-121-251.rdu2.redhat.com [10.10.121.251]) by smtp.corp.redhat.com (Postfix) with SMTP id 3E4D55ED42; Mon, 5 Nov 2018 18:16:26 +0000 (UTC) Date: Mon, 5 Nov 2018 13:16:25 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <20181105181353.39804-13-mst@redhat.com> References: <20181105181353.39804-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20181105181353.39804-1-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.45]); Mon, 05 Nov 2018 18:16:27 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 12/33] x86_iommu: move vtd_generate_msi_message in common file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "Singh, Brijesh" , Eduardo Habkost , Tom Lendacky , Peter Xu , Paolo Bonzini , Suravee Suthikulpanit , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Singh, Brijesh" The vtd_generate_msi_message() in intel-iommu is used to construct a MSI Message from IRQ. A similar function will be needed when we add interrupt remapping support in amd-iommu. Moving the function in common file to avoid the code duplication. Rename it to x86_iommu_irq_to_msi_message(). There is no logic changes in the code flow. Signed-off-by: Brijesh Singh Suggested-by: Peter Xu Reviewed-by: Eduardo Habkost Cc: Peter Xu Cc: "Michael S. Tsirkin" Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Cc: Marcel Apfelbaum Cc: Tom Lendacky Cc: Suravee Suthikulpanit Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/i386/intel_iommu.h | 59 ------------------------------- include/hw/i386/x86-iommu.h | 66 +++++++++++++++++++++++++++++++++++ hw/i386/intel_iommu.c | 32 +++-------------- hw/i386/x86-iommu.c | 24 +++++++++++++ 4 files changed, 94 insertions(+), 87 deletions(-) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index fbfedcb1c0..ed4e758273 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -66,8 +66,6 @@ typedef struct VTDIOTLBEntry VTDIOTLBEntry; typedef struct VTDBus VTDBus; typedef union VTD_IR_TableEntry VTD_IR_TableEntry; typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; -typedef struct VTDIrq VTDIrq; -typedef struct VTD_MSIMessage VTD_MSIMessage; =20 /* Context-Entry */ struct VTDContextEntry { @@ -197,63 +195,6 @@ union VTD_IR_MSIAddress { uint32_t data; }; =20 -/* Generic IRQ entry information */ -struct VTDIrq { - /* Used by both IOAPIC/MSI interrupt remapping */ - uint8_t trigger_mode; - uint8_t vector; - uint8_t delivery_mode; - uint32_t dest; - uint8_t dest_mode; - - /* only used by MSI interrupt remapping */ - uint8_t redir_hint; - uint8_t msi_addr_last_bits; -}; - -struct VTD_MSIMessage { - union { - struct { -#ifdef HOST_WORDS_BIGENDIAN - uint32_t __addr_head:12; /* 0xfee */ - uint32_t dest:8; - uint32_t __reserved:8; - uint32_t redir_hint:1; - uint32_t dest_mode:1; - uint32_t __not_used:2; -#else - uint32_t __not_used:2; - uint32_t dest_mode:1; - uint32_t redir_hint:1; - uint32_t __reserved:8; - uint32_t dest:8; - uint32_t __addr_head:12; /* 0xfee */ -#endif - uint32_t __addr_hi; - } QEMU_PACKED; - uint64_t msi_addr; - }; - union { - struct { -#ifdef HOST_WORDS_BIGENDIAN - uint16_t trigger_mode:1; - uint16_t level:1; - uint16_t __resved:3; - uint16_t delivery_mode:3; - uint16_t vector:8; -#else - uint16_t vector:8; - uint16_t delivery_mode:3; - uint16_t __resved:3; - uint16_t level:1; - uint16_t trigger_mode:1; -#endif - uint16_t __resved1; - } QEMU_PACKED; - uint32_t msi_data; - }; -}; - /* When IR is enabled, all MSI/MSI-X data bits should be zero */ #define VTD_IR_MSI_DATA (0) =20 diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h index 7c71fc7470..2b22a579a3 100644 --- a/include/hw/i386/x86-iommu.h +++ b/include/hw/i386/x86-iommu.h @@ -22,6 +22,7 @@ =20 #include "hw/sysbus.h" #include "hw/pci/pci.h" +#include "hw/pci/msi.h" =20 #define TYPE_X86_IOMMU_DEVICE ("x86-iommu") #define X86_IOMMU_DEVICE(obj) \ @@ -35,6 +36,8 @@ =20 typedef struct X86IOMMUState X86IOMMUState; typedef struct X86IOMMUClass X86IOMMUClass; +typedef struct X86IOMMUIrq X86IOMMUIrq; +typedef struct X86IOMMU_MSIMessage X86IOMMU_MSIMessage; =20 typedef enum IommuType { TYPE_INTEL, @@ -78,6 +81,63 @@ struct X86IOMMUState { QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */ }; =20 +/* Generic IRQ entry information when interrupt remapping is enabled */ +struct X86IOMMUIrq { + /* Used by both IOAPIC/MSI interrupt remapping */ + uint8_t trigger_mode; + uint8_t vector; + uint8_t delivery_mode; + uint32_t dest; + uint8_t dest_mode; + + /* only used by MSI interrupt remapping */ + uint8_t redir_hint; + uint8_t msi_addr_last_bits; +}; + +struct X86IOMMU_MSIMessage { + union { + struct { +#ifdef HOST_WORDS_BIGENDIAN + uint32_t __addr_head:12; /* 0xfee */ + uint32_t dest:8; + uint32_t __reserved:8; + uint32_t redir_hint:1; + uint32_t dest_mode:1; + uint32_t __not_used:2; +#else + uint32_t __not_used:2; + uint32_t dest_mode:1; + uint32_t redir_hint:1; + uint32_t __reserved:8; + uint32_t dest:8; + uint32_t __addr_head:12; /* 0xfee */ +#endif + uint32_t __addr_hi; + } QEMU_PACKED; + uint64_t msi_addr; + }; + union { + struct { +#ifdef HOST_WORDS_BIGENDIAN + uint16_t trigger_mode:1; + uint16_t level:1; + uint16_t __resved:3; + uint16_t delivery_mode:3; + uint16_t vector:8; +#else + uint16_t vector:8; + uint16_t delivery_mode:3; + uint16_t __resved:3; + uint16_t level:1; + uint16_t trigger_mode:1; +#endif + uint16_t __resved1; + } QEMU_PACKED; + uint32_t msi_data; + }; +}; + /** * x86_iommu_get_default - get default IOMMU device * @return: pointer to default IOMMU device @@ -110,4 +170,10 @@ void x86_iommu_iec_register_notifier(X86IOMMUState *io= mmu, void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global, uint32_t index, uint32_t mask); =20 +/** + * x86_iommu_irq_to_msi_message - Populate one MSIMessage from X86IOMMUIrq + * @X86IOMMUIrq: The IRQ information + * @out: Output MSI message + */ +void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *out); #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 015a6fc492..d97bcbc2f7 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2716,7 +2716,7 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint1= 6_t index, =20 /* Fetch IRQ information of specific IR index */ static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index, - VTDIrq *irq, uint16_t sid) + X86IOMMUIrq *irq, uint16_t sid) { VTD_IR_TableEntry irte =3D {}; int ret =3D 0; @@ -2745,30 +2745,6 @@ static int vtd_remap_irq_get(IntelIOMMUState *iommu,= uint16_t index, return 0; } =20 -/* Generate one MSI message from VTDIrq info */ -static void vtd_generate_msi_message(VTDIrq *irq, MSIMessage *msg_out) -{ - VTD_MSIMessage msg =3D {}; - - /* Generate address bits */ - msg.dest_mode =3D irq->dest_mode; - msg.redir_hint =3D irq->redir_hint; - msg.dest =3D irq->dest; - msg.__addr_hi =3D irq->dest & 0xffffff00; - msg.__addr_head =3D cpu_to_le32(0xfee); - /* Keep this from original MSI address bits */ - msg.__not_used =3D irq->msi_addr_last_bits; - - /* Generate data bits */ - msg.vector =3D irq->vector; - msg.delivery_mode =3D irq->delivery_mode; - msg.level =3D 1; - msg.trigger_mode =3D irq->trigger_mode; - - msg_out->address =3D msg.msi_addr; - msg_out->data =3D msg.msi_data; -} - /* Interrupt remapping for MSI/MSI-X entry */ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu, MSIMessage *origin, @@ -2778,7 +2754,7 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *i= ommu, int ret =3D 0; VTD_IR_MSIAddress addr; uint16_t index; - VTDIrq irq =3D {}; + X86IOMMUIrq irq =3D {}; =20 assert(origin && translated); =20 @@ -2857,8 +2833,8 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *i= ommu, */ irq.msi_addr_last_bits =3D addr.addr.__not_care; =20 - /* Translate VTDIrq to MSI message */ - vtd_generate_msi_message(&irq, translated); + /* Translate X86IOMMUIrq to MSI message */ + x86_iommu_irq_to_msi_message(&irq, translated); =20 out: trace_vtd_ir_remap_msi(origin->address, origin->data, diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c index 7440cb8d60..abc3c03158 100644 --- a/hw/i386/x86-iommu.c +++ b/hw/i386/x86-iommu.c @@ -53,6 +53,30 @@ void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool= global, } } =20 +/* Generate one MSI message from VTDIrq info */ +void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *msg_out) +{ + X86IOMMU_MSIMessage msg =3D {}; + + /* Generate address bits */ + msg.dest_mode =3D irq->dest_mode; + msg.redir_hint =3D irq->redir_hint; + msg.dest =3D irq->dest; + msg.__addr_hi =3D irq->dest & 0xffffff00; + msg.__addr_head =3D cpu_to_le32(0xfee); + /* Keep this from original MSI address bits */ + msg.__not_used =3D irq->msi_addr_last_bits; + + /* Generate data bits */ + msg.vector =3D irq->vector; + msg.delivery_mode =3D irq->delivery_mode; + msg.level =3D 1; + msg.trigger_mode =3D irq->trigger_mode; + + msg_out->address =3D msg.msi_addr; + msg_out->data =3D msg.msi_data; +} + /* Default X86 IOMMU device */ static X86IOMMUState *x86_iommu_default =3D NULL; =20 --=20 MST