From nobody Thu Nov 6 14:31:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541382293854337.00646490820475; Sun, 4 Nov 2018 17:44:53 -0800 (PST) Received: from localhost ([::1]:60854 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJTwi-0001Hw-F4 for importer@patchew.org; Sun, 04 Nov 2018 20:44:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46988) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJTuf-0007Li-A2 for qemu-devel@nongnu.org; Sun, 04 Nov 2018 20:42:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJTue-0002px-39 for qemu-devel@nongnu.org; Sun, 04 Nov 2018 20:42:45 -0500 Received: from mga18.intel.com ([134.134.136.126]:7954) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gJTua-0002Fx-5C; Sun, 04 Nov 2018 20:42:40 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Nov 2018 17:42:25 -0800 Received: from emurphy1-mobl1.ger.corp.intel.com (HELO localhost.localdomain) ([10.252.26.250]) by fmsmga005.fm.intel.com with ESMTP; 04 Nov 2018 17:42:20 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,466,1534834800"; d="scan'208";a="277074346" From: Samuel Ortiz To: qemu-devel@nongnu.org Date: Mon, 5 Nov 2018 02:40:32 +0100 Message-Id: <20181105014047.26447-10-sameo@linux.intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181105014047.26447-1-sameo@linux.intel.com> References: <20181105014047.26447-1-sameo@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.126 Subject: [Qemu-devel] [PATCH v5 09/24] hw: i386: Move PCI host definitions to pci_host.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Stefano Stabellini , Eduardo Habkost , "Michael S. Tsirkin" , Shannon Zhao , Igor Mammedov , qemu-arm@nongnu.org, Paolo Bonzini , Anthony Perard , xen-devel@lists.xenproject.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The PCI hole properties are not pc or i386 specific. They belong to the PCI host header instead. Signed-off-by: Samuel Ortiz --- include/hw/i386/pc.h | 5 ----- include/hw/pci/pci_host.h | 6 ++++++ 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index fed136fcdd..bbbdb33ea3 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -182,11 +182,6 @@ void pc_acpi_init(const char *default_dsdt); =20 void pc_guest_info_init(PCMachineState *pcms); =20 -#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" -#define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" -#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" -#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" -#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" =20 diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index ba31595fc7..e343f4d9ca 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -38,6 +38,12 @@ #define PCI_HOST_BRIDGE_GET_CLASS(obj) \ OBJECT_GET_CLASS(PCIHostBridgeClass, (obj), TYPE_PCI_HOST_BRIDGE) =20 +#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" +#define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" +#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" +#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" +#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" + struct PCIHostState { SysBusDevice busdev; =20 --=20 2.19.1