From nobody Mon Feb 9 23:03:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541179279883906.2652674799106; Fri, 2 Nov 2018 10:21:19 -0700 (PDT) Received: from localhost ([::1]:52783 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gId8I-0003PT-H1 for importer@patchew.org; Fri, 02 Nov 2018 13:21:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50841) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gId63-0001yc-Do for qemu-devel@nongnu.org; Fri, 02 Nov 2018 13:19:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gId62-0004Dy-1w for qemu-devel@nongnu.org; Fri, 02 Nov 2018 13:18:59 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52250) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gId61-0002Zn-3p for qemu-devel@nongnu.org; Fri, 02 Nov 2018 13:18:57 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gId3v-0003aW-21 for qemu-devel@nongnu.org; Fri, 02 Nov 2018 17:16:47 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 17:16:34 +0000 Message-Id: <20181102171638.24069-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181102171638.24069-1-peter.maydell@linaro.org> References: <20181102171638.24069-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/10] strongarm: mask off high[31:28] bits from dir and state registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Prasad J Pandit The high[31:28] bits of 'direction' and 'state' registers of SA-1100/SA-1110 device are reserved. Setting them may lead to OOB 's->handler[]' array access issue. Mask off [31:28] bits to avoid it. Reported-by: Moguofang Signed-off-by: Prasad J Pandit Message-id: 20181030114635.31232-1-ppandit@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/strongarm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index ec2627374d0..644a9c45b4e 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -587,12 +587,12 @@ static void strongarm_gpio_write(void *opaque, hwaddr= offset, =20 switch (offset) { case GPDR: /* GPIO Pin-Direction registers */ - s->dir =3D value; + s->dir =3D value & 0x0fffffff; strongarm_gpio_handler_update(s); break; =20 case GPSR: /* GPIO Pin-Output Set registers */ - s->olevel |=3D value; + s->olevel |=3D value & 0x0fffffff; strongarm_gpio_handler_update(s); break; =20 --=20 2.19.1