From nobody Wed Apr 16 16:47:02 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541179389162186.67218691728738; Fri, 2 Nov 2018 10:23:09 -0700 (PDT) Received: from localhost ([::1]:52793 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIdA3-0004p8-VB for importer@patchew.org; Fri, 02 Nov 2018 13:23:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51145) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gId6F-0002GR-1E for qemu-devel@nongnu.org; Fri, 02 Nov 2018 13:19:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gId6A-0004P5-Qq for qemu-devel@nongnu.org; Fri, 02 Nov 2018 13:19:10 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52250) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gId69-0002Zn-Ry for qemu-devel@nongnu.org; Fri, 02 Nov 2018 13:19:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gId3r-0003Zc-ES for qemu-devel@nongnu.org; Fri, 02 Nov 2018 17:16:43 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 17:16:30 +0000 Message-Id: <20181102171638.24069-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181102171638.24069-1-peter.maydell@linaro.org> References: <20181102171638.24069-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/10] hw/char: Implement nRF51 SoC UART X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Julia Suvorova Not implemented: CTS/NCTS, PSEL*. Signed-off-by: Julia Suvorova Reviewed-by: Stefan Hajnoczi Signed-off-by: Peter Maydell --- hw/char/Makefile.objs | 1 + include/hw/char/nrf51_uart.h | 78 +++++++++ hw/char/nrf51_uart.c | 330 +++++++++++++++++++++++++++++++++++ hw/char/trace-events | 4 + 4 files changed, 413 insertions(+) create mode 100644 include/hw/char/nrf51_uart.h create mode 100644 hw/char/nrf51_uart.c diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index b5705312910..c4947d7ae7b 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -1,5 +1,6 @@ common-obj-$(CONFIG_IPACK) +=3D ipoctal232.o common-obj-$(CONFIG_ESCC) +=3D escc.o +common-obj-$(CONFIG_NRF51_SOC) +=3D nrf51_uart.o common-obj-$(CONFIG_PARALLEL) +=3D parallel.o common-obj-$(CONFIG_PARALLEL) +=3D parallel-isa.o common-obj-$(CONFIG_PL011) +=3D pl011.o diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h new file mode 100644 index 00000000000..e3ecb7c81c2 --- /dev/null +++ b/include/hw/char/nrf51_uart.h @@ -0,0 +1,78 @@ +/* + * nRF51 SoC UART emulation + * + * Copyright (c) 2018 Julia Suvorova + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#ifndef NRF51_UART_H +#define NRF51_UART_H + +#include "hw/sysbus.h" +#include "chardev/char-fe.h" +#include "hw/registerfields.h" + +#define UART_FIFO_LENGTH 6 +#define UART_BASE 0x40002000 +#define UART_SIZE 0x1000 + +#define TYPE_NRF51_UART "nrf51_soc.uart" +#define NRF51_UART(obj) OBJECT_CHECK(NRF51UARTState, (obj), TYPE_NRF51_UAR= T) + +REG32(UART_STARTRX, 0x000) +REG32(UART_STOPRX, 0x004) +REG32(UART_STARTTX, 0x008) +REG32(UART_STOPTX, 0x00C) +REG32(UART_SUSPEND, 0x01C) + +REG32(UART_CTS, 0x100) +REG32(UART_NCTS, 0x104) +REG32(UART_RXDRDY, 0x108) +REG32(UART_TXDRDY, 0x11C) +REG32(UART_ERROR, 0x124) +REG32(UART_RXTO, 0x144) + +REG32(UART_INTEN, 0x300) + FIELD(UART_INTEN, CTS, 0, 1) + FIELD(UART_INTEN, NCTS, 1, 1) + FIELD(UART_INTEN, RXDRDY, 2, 1) + FIELD(UART_INTEN, TXDRDY, 7, 1) + FIELD(UART_INTEN, ERROR, 9, 1) + FIELD(UART_INTEN, RXTO, 17, 1) +REG32(UART_INTENSET, 0x304) +REG32(UART_INTENCLR, 0x308) +REG32(UART_ERRORSRC, 0x480) +REG32(UART_ENABLE, 0x500) +REG32(UART_PSELRTS, 0x508) +REG32(UART_PSELTXD, 0x50C) +REG32(UART_PSELCTS, 0x510) +REG32(UART_PSELRXD, 0x514) +REG32(UART_RXD, 0x518) +REG32(UART_TXD, 0x51C) +REG32(UART_BAUDRATE, 0x524) +REG32(UART_CONFIG, 0x56C) + +typedef struct NRF51UARTState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + CharBackend chr; + qemu_irq irq; + guint watch_tag; + + uint8_t rx_fifo[UART_FIFO_LENGTH]; + unsigned int rx_fifo_pos; + unsigned int rx_fifo_len; + + uint32_t reg[0x56C]; + + bool rx_started; + bool tx_started; + bool pending_tx_byte; + bool enabled; +} NRF51UARTState; + +#endif diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c new file mode 100644 index 00000000000..2f5fae61671 --- /dev/null +++ b/hw/char/nrf51_uart.c @@ -0,0 +1,330 @@ +/* + * nRF51 SoC UART emulation + * + * See nRF51 Series Reference Manual, "29 Universal Asynchronous + * Receiver/Transmitter" for hardware specifications: + * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * + * Copyright (c) 2018 Julia Suvorova + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/char/nrf51_uart.h" +#include "trace.h" + +static void nrf51_uart_update_irq(NRF51UARTState *s) +{ + bool irq =3D false; + + irq |=3D (s->reg[R_UART_RXDRDY] && + (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK)); + irq |=3D (s->reg[R_UART_TXDRDY] && + (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK)); + irq |=3D (s->reg[R_UART_ERROR] && + (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK)); + irq |=3D (s->reg[R_UART_RXTO] && + (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK)); + + qemu_set_irq(s->irq, irq); +} + +static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + uint64_t r; + + if (!s->enabled) { + return 0; + } + + switch (addr) { + case A_UART_RXD: + r =3D s->rx_fifo[s->rx_fifo_pos]; + if (s->rx_started && s->rx_fifo_len) { + s->rx_fifo_pos =3D (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH; + s->rx_fifo_len--; + if (s->rx_fifo_len) { + s->reg[R_UART_RXDRDY] =3D 1; + nrf51_uart_update_irq(s); + } + qemu_chr_fe_accept_input(&s->chr); + } + break; + case A_UART_INTENSET: + case A_UART_INTENCLR: + case A_UART_INTEN: + r =3D s->reg[R_UART_INTEN]; + break; + default: + r =3D s->reg[addr / 4]; + break; + } + + trace_nrf51_uart_read(addr, r, size); + + return r; +} + +static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *o= paque) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + int r; + uint8_t c =3D s->reg[R_UART_TXD]; + + s->watch_tag =3D 0; + + r =3D qemu_chr_fe_write(&s->chr, &c, 1); + if (r <=3D 0) { + s->watch_tag =3D qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HU= P, + uart_transmit, s); + if (!s->watch_tag) { + /* The hardware has no transmit error reporting, + * so silently drop the byte + */ + goto buffer_drained; + } + return FALSE; + } + +buffer_drained: + s->reg[R_UART_TXDRDY] =3D 1; + s->pending_tx_byte =3D false; + return FALSE; +} + +static void uart_cancel_transmit(NRF51UARTState *s) +{ + if (s->watch_tag) { + g_source_remove(s->watch_tag); + s->watch_tag =3D 0; + } +} + +static void uart_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + + trace_nrf51_uart_write(addr, value, size); + + if (!s->enabled && (addr !=3D A_UART_ENABLE)) { + return; + } + + switch (addr) { + case A_UART_TXD: + if (!s->pending_tx_byte && s->tx_started) { + s->reg[R_UART_TXD] =3D value; + s->pending_tx_byte =3D true; + uart_transmit(NULL, G_IO_OUT, s); + } + break; + case A_UART_INTEN: + s->reg[R_UART_INTEN] =3D value; + break; + case A_UART_INTENSET: + s->reg[R_UART_INTEN] |=3D value; + break; + case A_UART_INTENCLR: + s->reg[R_UART_INTEN] &=3D ~value; + break; + case A_UART_TXDRDY ... A_UART_RXTO: + s->reg[addr / 4] =3D value; + break; + case A_UART_ERRORSRC: + s->reg[addr / 4] &=3D ~value; + break; + case A_UART_RXD: + break; + case A_UART_RXDRDY: + if (value =3D=3D 0) { + s->reg[R_UART_RXDRDY] =3D 0; + } + break; + case A_UART_STARTTX: + if (value =3D=3D 1) { + s->tx_started =3D true; + } + break; + case A_UART_STARTRX: + if (value =3D=3D 1) { + s->rx_started =3D true; + } + break; + case A_UART_ENABLE: + if (value) { + if (value =3D=3D 4) { + s->enabled =3D true; + } + break; + } + s->enabled =3D false; + value =3D 1; + /* fall through */ + case A_UART_SUSPEND: + case A_UART_STOPTX: + if (value =3D=3D 1) { + s->tx_started =3D false; + } + /* fall through */ + case A_UART_STOPRX: + if (addr !=3D A_UART_STOPTX && value =3D=3D 1) { + s->rx_started =3D false; + s->reg[R_UART_RXTO] =3D 1; + } + break; + default: + s->reg[addr / 4] =3D value; + break; + } + nrf51_uart_update_irq(s); +} + +static const MemoryRegionOps uart_ops =3D { + .read =3D uart_read, + .write =3D uart_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void nrf51_uart_reset(DeviceState *dev) +{ + NRF51UARTState *s =3D NRF51_UART(dev); + + s->pending_tx_byte =3D 0; + + uart_cancel_transmit(s); + + memset(s->reg, 0, sizeof(s->reg)); + + s->reg[R_UART_PSELRTS] =3D 0xFFFFFFFF; + s->reg[R_UART_PSELTXD] =3D 0xFFFFFFFF; + s->reg[R_UART_PSELCTS] =3D 0xFFFFFFFF; + s->reg[R_UART_PSELRXD] =3D 0xFFFFFFFF; + s->reg[R_UART_BAUDRATE] =3D 0x4000000; + + s->rx_fifo_len =3D 0; + s->rx_fifo_pos =3D 0; + s->rx_started =3D false; + s->tx_started =3D false; + s->enabled =3D false; +} + +static void uart_receive(void *opaque, const uint8_t *buf, int size) +{ + + NRF51UARTState *s =3D NRF51_UART(opaque); + int i; + + if (size =3D=3D 0 || s->rx_fifo_len >=3D UART_FIFO_LENGTH) { + return; + } + + for (i =3D 0; i < size; i++) { + uint32_t pos =3D (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LEN= GTH; + s->rx_fifo[pos] =3D buf[i]; + s->rx_fifo_len++; + } + + s->reg[R_UART_RXDRDY] =3D 1; + nrf51_uart_update_irq(s); +} + +static int uart_can_receive(void *opaque) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + + return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0; +} + +static void uart_event(void *opaque, int event) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + + if (event =3D=3D CHR_EVENT_BREAK) { + s->reg[R_UART_ERRORSRC] |=3D 3; + s->reg[R_UART_ERROR] =3D 1; + nrf51_uart_update_irq(s); + } +} + +static void nrf51_uart_realize(DeviceState *dev, Error **errp) +{ + NRF51UARTState *s =3D NRF51_UART(dev); + + qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, + uart_event, NULL, s, NULL, true); +} + +static void nrf51_uart_init(Object *obj) +{ + NRF51UARTState *s =3D NRF51_UART(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &uart_ops, s, + "nrf51_soc.uart", UART_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static int nrf51_uart_post_load(void *opaque, int version_id) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + + if (s->pending_tx_byte) { + s->watch_tag =3D qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HU= P, + uart_transmit, s); + } + + return 0; +} + +static const VMStateDescription nrf51_uart_vmstate =3D { + .name =3D "nrf51_soc.uart", + .post_load =3D nrf51_uart_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C), + VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH), + VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState), + VMSTATE_UINT32(rx_fifo_len, NRF51UARTState), + VMSTATE_BOOL(rx_started, NRF51UARTState), + VMSTATE_BOOL(tx_started, NRF51UARTState), + VMSTATE_BOOL(pending_tx_byte, NRF51UARTState), + VMSTATE_BOOL(enabled, NRF51UARTState), + VMSTATE_END_OF_LIST() + } +}; + +static Property nrf51_uart_properties[] =3D { + DEFINE_PROP_CHR("chardev", NRF51UARTState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void nrf51_uart_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D nrf51_uart_reset; + dc->realize =3D nrf51_uart_realize; + dc->props =3D nrf51_uart_properties; + dc->vmsd =3D &nrf51_uart_vmstate; +} + +static const TypeInfo nrf51_uart_info =3D { + .name =3D TYPE_NRF51_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51UARTState), + .instance_init =3D nrf51_uart_init, + .class_init =3D nrf51_uart_class_init +}; + +static void nrf51_uart_register_types(void) +{ + type_register_static(&nrf51_uart_info); +} + +type_init(nrf51_uart_register_types) diff --git a/hw/char/trace-events b/hw/char/trace-events index b64213d4dd1..de34a74399b 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -73,3 +73,7 @@ cmsdk_apb_uart_receive(uint8_t c) "CMSDK APB UART: got ch= aracter 0x%x from backe cmsdk_apb_uart_tx_pending(void) "CMSDK APB UART: character send to backend= pending" cmsdk_apb_uart_tx(uint8_t c) "CMSDK APB UART: character 0x%x sent to backe= nd" cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1" + +# hw/char/nrf51_uart.c +nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" P= RIx64 " value 0x%" PRIx64 " size %u" +nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0= x%" PRIx64 " value 0x%" PRIx64 " size %u" --=20 2.19.1