From nobody Wed May 1 04:32:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541170607150239.8856858721905; Fri, 2 Nov 2018 07:56:47 -0700 (PDT) Received: from localhost ([::1]:52032 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIasP-0003Ma-T0 for importer@patchew.org; Fri, 02 Nov 2018 10:56:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIaqW-0002FE-Ff for qemu-devel@nongnu.org; Fri, 02 Nov 2018 10:54:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gIaqV-0003Hg-88 for qemu-devel@nongnu.org; Fri, 02 Nov 2018 10:54:48 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:42483) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gIaqS-0003Eg-Lz for qemu-devel@nongnu.org; Fri, 02 Nov 2018 10:54:45 -0400 Received: by mail-wr1-x443.google.com with SMTP id y15-v6so2268974wru.9 for ; Fri, 02 Nov 2018 07:54:40 -0700 (PDT) Received: from cloudburst.Home ([2a02:c7f:504f:6300:a3de:88d8:75ae:bf4c]) by smtp.gmail.com with ESMTPSA id l5-v6sm10698454wrv.84.2018.11.02.07.54.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 02 Nov 2018 07:54:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PpLXpocO/xsWRefCIa8us272LlmFyb71GTp1lXZH/b8=; b=NlzmD2um85jnNtbQreq82Y8JljxMO30WfdEPB+lQBBWK1BunEJzJOAIaKCCTbRb3IR zoVGyO5XX8zwLHuK1vcOokvHfXLnIyQ6q2NwnYfe/uV1FI7cx2E6+7iA4yjKsgrgZf4g dlGBZkWCT9Z3n+PwWq1DVOPQy8J7Z1JjGk+7c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PpLXpocO/xsWRefCIa8us272LlmFyb71GTp1lXZH/b8=; b=uQR7GGZW5/84RkK2s8g7b8ce89in9Yf4Cyy8vF7GJVWXYjGDubOdKoz024ATrYjVVO KCU22QSdViO0nBfeuujYOQpQ9bRN/VtIpKp9zeexwzgfFn8m7io89U2V4lruQvYPkE/s hYHPPhuObienqSNE2r38Vqu1upxPqJYk52oHvhYCJbC63u6LCXzeUibV0OOVfqd1x/PC KA/RiuqC30p/M7T7W4ahyQGKV9xrYbjwnRxZT4NCNnbT0AMV7fLBRfqpVgEpIn+vJDcU 1/6dR3a3AS1x3lOOBwBnG6gbtvP+k+0JXL9oeEmOuh3lEPrVrIobjnOAE0D9IOibQNte 0Rsg== X-Gm-Message-State: AGRZ1gJnS2PkRD1gPLu7hdmDyd6kTBpJ4VZ/syEHq5LxeqG8u64GbqMM IjNrLxUjhy+wFwPfHGqnBNGTPjeiQWU= X-Google-Smtp-Source: AJdET5fHH65mPmC+nfk9eNJidy4E0bdv3jRrYAvuzEXmR6TDOEtWxX3omqqOZo2/vODNMLg13MVetw== X-Received: by 2002:a5d:6585:: with SMTP id q5-v6mr10150692wru.141.1541170478979; Fri, 02 Nov 2018 07:54:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 14:54:29 +0000 Message-Id: <20181102145433.4553-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181102145433.4553-1-richard.henderson@linaro.org> References: <20181102145433.4553-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v2 1/5] target/arm: Install ARMISARegisters from kvm host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ID registers are replacing (some of) the feature bits. We need (some of) these values to determine the set of data to be handled during migration. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/kvm_arm.h | 1 + target/arm/kvm.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 21c0129da2..6393455b1d 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -183,6 +183,7 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); * by asking the host kernel) */ typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; uint64_t features; uint32_t target; const char *dtb_compatible; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 09a86e2820..44dd0ce6ce 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -158,6 +158,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) =20 cpu->kvm_target =3D arm_host_cpu_features.target; cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; + cpu->isar =3D arm_host_cpu_features.isar; env->features =3D arm_host_cpu_features.features; } =20 --=20 2.17.2 From nobody Wed May 1 04:32:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541170621466583.6264047733576; Fri, 2 Nov 2018 07:57:01 -0700 (PDT) Received: from localhost ([::1]:52033 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIase-0003YR-52 for importer@patchew.org; Fri, 02 Nov 2018 10:57:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56714) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIaqX-0002Ft-Ap for qemu-devel@nongnu.org; Fri, 02 Nov 2018 10:54:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gIaqW-0003Ip-0G for qemu-devel@nongnu.org; Fri, 02 Nov 2018 10:54:49 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:53716) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gIaqV-0003F2-NT for qemu-devel@nongnu.org; Fri, 02 Nov 2018 10:54:47 -0400 Received: by mail-wm1-x341.google.com with SMTP id v24-v6so2237479wmh.3 for ; Fri, 02 Nov 2018 07:54:41 -0700 (PDT) Received: from cloudburst.Home ([2a02:c7f:504f:6300:a3de:88d8:75ae:bf4c]) by smtp.gmail.com with ESMTPSA id l5-v6sm10698454wrv.84.2018.11.02.07.54.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 02 Nov 2018 07:54:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ffmgcNzfXibNpDQsqKV4PQiksneuZIsACAOYCKu/8+E=; b=FsqeCJ3xN7NjX/11jKkWQcXlrZiBFo0WbKa+EOUcDVOZpXQ4NtumdEEgGe0JnCPUJl yxh++xHkIT9+RgY9cAjJ4KW1PmTRM5h5cmDD65GphmCjANSOIm/50RzKrPLfbw6MLH9W /EaB7YrtFR7yHbKq568OGN6fK2NUd0uo5cVfI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ffmgcNzfXibNpDQsqKV4PQiksneuZIsACAOYCKu/8+E=; b=c3sKHCERq/e5Dj18CF6v+8EOTafk9UY/JmFZ/d5egmQRQ/Qz4FJPBGjuC21qhPPA04 a1Z1onJj80K+FbpvWoYplFIBjU2fGnV8yWQggyof/qHTv97OQrTbcEK+Ba74K2Tm7uIk mylDoxW9d0vpnrYhleQAozZK8Of0Kbf0dn4SQ6ZjRlciXi+EYnQiS12w1JViVR1pxyMx xKuBi8sSrDlq+Bi2RjafQdV6m1c6NldSf/wbhV2XzZK95pJyBdCdp7z9/AQciYQ7F2LO 55iSjGZKOYvkIB8nMTK0K9jFxOs5YFBLnvKFDYR1a9RioV1ytBO4e92os9MCGz2Elmad BlBg== X-Gm-Message-State: AGRZ1gLEcSU9PR0U93OLTS8U67/wKC0S30+ClNjQYqZC2zbQTxDayPUv PFHOQo23pBcJrRYBM02g3sA5ZBXqjQM= X-Google-Smtp-Source: AJdET5dIQbxL2+ZZHr26D6/jKvyBHo8cAOQuZv8XUZTaXICPwI4OhTXogC/WkA1cPfqgOqid4so3/w== X-Received: by 2002:a1c:3492:: with SMTP id b140-v6mr19250wma.115.1541170479869; Fri, 02 Nov 2018 07:54:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 14:54:30 +0000 Message-Id: <20181102145433.4553-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181102145433.4553-1-richard.henderson@linaro.org> References: <20181102145433.4553-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v2 2/5] target/arm: Fill in ARMISARegisters for kvm64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 69 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 67 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5de8ff0ac5..d4d4e63140 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -443,17 +443,40 @@ static inline void unset_feature(uint64_t *features, = int feature) *features &=3D ~(1ULL << feature); } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + uint64_t ret; + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)&ret }; + int err; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + err =3D ioctl(fd, KVM_GET_ONE_REG, &idreg); + if (err < 0) { + return -1; + } + *pret =3D ret; + return 0; +} + +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. - * For AArch64 we currently don't care about ID registers at - * all; we just want to know the CPU type. */ int fdarray[3]; uint64_t features =3D 0; + int err =3D 0; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. Fortunately these old kernels @@ -474,8 +497,50 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) ahcf->target =3D init.target; ahcf->dtb_compatible =3D "arm,arm-v8"; =20 + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, + ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, + ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, + ARM64_SYS_REG(3, 0, 0, 4, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, + ARM64_SYS_REG(3, 0, 0, 4, 1)); + + /* + * Note that if AArch32 support is not present in the host, + * the AArch32 sysregs are present to be read, but will + * return UNKNOWN values. This is neither better nor worse + * than skipping the reads and leaving 0, as we must avoid + * considering the values in every case. + */ + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM64_SYS_REG(3, 0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM64_SYS_REG(3, 0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM64_SYS_REG(3, 0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM64_SYS_REG(3, 0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM64_SYS_REG(3, 0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM64_SYS_REG(3, 0, 0, 2, 7)); + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + ARM64_SYS_REG(3, 0, 0, 3, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + ARM64_SYS_REG(3, 0, 0, 3, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + ARM64_SYS_REG(3, 0, 0, 3, 2)); + kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 + if (err < 0) { + return false; + } + /* We can assume any KVM supporting CPU is at least a v8 * with VFPv4+Neon; this in turn implies most of the other * feature bits. --=20 2.17.2 From nobody Wed May 1 04:32:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154117071750942.05166810410094; Fri, 2 Nov 2018 07:58:37 -0700 (PDT) Received: from localhost ([::1]:52046 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIauC-0006Hz-EV for importer@patchew.org; Fri, 02 Nov 2018 10:58:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56622) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIaqV-0002EK-CO for qemu-devel@nongnu.org; Fri, 02 Nov 2018 10:54:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gIaqT-0003Gi-AG for qemu-devel@nongnu.org; Fri, 02 Nov 2018 10:54:47 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:55791) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gIaqR-0003FD-CU for qemu-devel@nongnu.org; Fri, 02 Nov 2018 10:54:44 -0400 Received: by mail-wm1-x342.google.com with SMTP id s10-v6so2225026wmc.5 for ; Fri, 02 Nov 2018 07:54:42 -0700 (PDT) Received: from cloudburst.Home ([2a02:c7f:504f:6300:a3de:88d8:75ae:bf4c]) by smtp.gmail.com with ESMTPSA id l5-v6sm10698454wrv.84.2018.11.02.07.54.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 02 Nov 2018 07:54:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wAAqQsydo91GFkx0Iu9I74oQUpqdHqV7ni9QirCbmpY=; b=UYvBjr3z8o1dCoQo5frgyu7JKU+sxs/+594og/R7epdFtVon5VsHsxFftKoK3ZUO/q taM1Tu9gs/rBnCvDOfjxdJJb+jYa/ae432U9pXWDpdteEJ2XlOWpYSSjV3+jqDYA5SBd cLB//WbNeKx8ugwCGd7aXEew8S02Gy4c6YCAg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wAAqQsydo91GFkx0Iu9I74oQUpqdHqV7ni9QirCbmpY=; b=P2f1K7R/KKMbi55lzfNh9qnLeItcCS2aF2wSAPQ/bHw/vjgWA152eoKxz6RKLP97Y9 R6tW7aB1+GrR7Rf8VkwHV7Z1rUOiKFISJkuWuecfmKcocjtmnqRXpkMTCkTn446xpbl4 GhzGixGLnXWgCJ+/3ypBRYBFkn9C67OLAaW10y8c9++BQ27M8kYBmeuO6pleCfWpegHT TBwq0vkBlCM1ytpxeghpcR25uUuFAxcxbA5aZzLg/HSPodhdvtbJeTpYiBflyA2TBPkn N/kXiBPdtIzl0WAW7cHZFiKVRvdOBxj9ZWWOj/7N91c87F+iNjilncqpiD/b6BWQ69CM 5UFQ== X-Gm-Message-State: AGRZ1gKl8P4Xj3cU364vpeu944cLL9S39gpdlUxUbJaACv0y6v/i6ijI RYpgNh+Hed/26MxQwwv/kfHOHs3g7MU= X-Google-Smtp-Source: AJdET5dc3QWpDqVmreYKArzcD+vZMEloFlhy99OPaInvVJP8CRx7aADZMigPcBz0twh8HfuA+YbrlQ== X-Received: by 2002:a1c:49c2:: with SMTP id w185-v6mr38843wma.144.1541170480873; Fri, 02 Nov 2018 07:54:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 14:54:31 +0000 Message-Id: <20181102145433.4553-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181102145433.4553-1-richard.henderson@linaro.org> References: <20181102145433.4553-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v2 3/5] target/arm: Introduce read_sys_reg32 for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Assert that the value to be written is the correct size. No change in functionality here, just mirroring the same function from kvm64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/kvm32.c | 41 ++++++++++++++++------------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 0f1e94c7b5..de573f9aa8 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -28,6 +28,14 @@ static inline void set_feature(uint64_t *features, int f= eature) *features |=3D 1ULL << feature; } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U32); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -35,9 +43,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. */ - int i, ret, fdarray[3]; + int err =3D 0, fdarray[3]; uint32_t midr, id_pfr0, mvfr1; uint64_t features =3D 0; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. @@ -47,23 +56,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) QEMU_KVM_ARM_TARGET_NONE }; struct kvm_vcpu_init init; - struct kvm_one_reg idregs[] =3D { - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0), - .addr =3D (uintptr_t)&midr, - }, - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0), - .addr =3D (uintptr_t)&id_pfr0, - }, - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1, - .addr =3D (uintptr_t)&mvfr1, - }, - }; =20 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { return false; @@ -77,16 +69,15 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) */ ahcf->dtb_compatible =3D "arm,arm-v7"; =20 - for (i =3D 0; i < ARRAY_SIZE(idregs); i++) { - ret =3D ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]); - if (ret) { - break; - } - } + err |=3D read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); + err |=3D read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, = 0)); + err |=3D read_sys_reg32(fdarray[2], &mvfr1, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 - if (ret) { + if (err < 0) { return false; } =20 --=20 2.17.2 From nobody Wed May 1 04:32:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 02 Nov 2018 07:54:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 14:54:32 +0000 Message-Id: <20181102145433.4553-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181102145433.4553-1-richard.henderson@linaro.org> References: <20181102145433.4553-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v2 4/5] target/arm: Fill in ARMISARegisters for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/kvm32.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index de573f9aa8..9ededa3c73 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -44,7 +44,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ah= cf) * and then query that CPU for the relevant ID registers. */ int err =3D 0, fdarray[3]; - uint32_t midr, id_pfr0, mvfr1; + uint32_t midr, id_pfr0; uint64_t features =3D 0; =20 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -71,9 +71,32 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) =20 err |=3D read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); err |=3D read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, = 0)); - err |=3D read_sys_reg32(fdarray[2], &mvfr1, + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM_CP15_REG32(0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM_CP15_REG32(0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM_CP15_REG32(0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM_CP15_REG32(0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM_CP15_REG32(0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM_CP15_REG32(0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM_CP15_REG32(0, 0, 2, 7)); + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); + /* + * FIXME: There is not yet a way to read MVFR2. + * Fortunately there is not yet anything in there that affects migrati= on. + */ =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 @@ -95,13 +118,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) if (extract32(id_pfr0, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_THUMB2EE); } - if (extract32(mvfr1, 20, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 20, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } - if (extract32(mvfr1, 12, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(mvfr1, 28, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 28, 4) =3D=3D 1) { /* FMAC support implies VFPv4 */ set_feature(&features, ARM_FEATURE_VFP4); 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Fri, 02 Nov 2018 07:54:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 14:54:33 +0000 Message-Id: <20181102145433.4553-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181102145433.4553-1-richard.henderson@linaro.org> References: <20181102145433.4553-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v2 5/5] target/arm: Convert t32ee from feature bit to isar3 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 +++++- linux-user/elfload.c | 2 +- target/arm/cpu.c | 4 ---- target/arm/helper.c | 2 +- target/arm/kvm32.c | 3 --- target/arm/machine.c | 3 +-- 6 files changed, 8 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8e6779936e..895f9909d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1575,7 +1575,6 @@ enum arm_features { ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE, ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ ARM_FEATURE_V4T, @@ -3172,6 +3171,11 @@ static inline bool isar_feature_jazelle(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; } =20 +static inline bool isar_feature_t32ee(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar3, ID_ISAR3, T32EE) !=3D 0; +} + static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) !=3D 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5bccd2e243..a3503c83c9 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -466,7 +466,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); - GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + GET_FEATURE_ID(t32ee, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8f16e96b6c..e08a2d2d79 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1440,7 +1440,6 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr =3D 0x410fc080; @@ -1509,7 +1508,6 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different @@ -1572,7 +1570,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); @@ -1618,7 +1615,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ea95b0815..bea4d5350d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5455,7 +5455,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + if (cpu_isar_feature(t32ee, cpu)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 9ededa3c73..8b2c9b3075 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -115,9 +115,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) set_feature(&features, ARM_FEATURE_VFP3); set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 - if (extract32(id_pfr0, 12, 4) =3D=3D 1) { - set_feature(&features, ARM_FEATURE_THUMB2EE); - } if (extract32(ahcf->isar.mvfr1, 20, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } diff --git a/target/arm/machine.c b/target/arm/machine.c index 239fe4e84d..07f904709a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -321,9 +321,8 @@ static const VMStateDescription vmstate_m =3D { static bool thumb2ee_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_THUMB2EE); + return cpu_isar_feature(t32ee, cpu); } =20 static const VMStateDescription vmstate_thumb2ee =3D { --=20 2.17.2