From nobody Sun Apr 28 21:06:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541166330158649.2940133251835; Fri, 2 Nov 2018 06:45:30 -0700 (PDT) Received: from localhost ([::1]:51778 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIZlQ-0002En-Sl for importer@patchew.org; Fri, 02 Nov 2018 09:45:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIZhn-0007AG-8U for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gIZhl-0007Nl-A2 for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:43 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:53350) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gIZhk-0007Ax-5Y for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:40 -0400 Received: by mail-wm1-x342.google.com with SMTP id v24-v6so2038679wmh.3 for ; Fri, 02 Nov 2018 06:41:20 -0700 (PDT) Received: from cloudburst.Home ([2a02:c7f:504f:6300:a3de:88d8:75ae:bf4c]) by smtp.gmail.com with ESMTPSA id e10-v6sm1629686wrp.56.2018.11.02.06.41.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 02 Nov 2018 06:41:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0ayiDrZA6aBx9vXHSLgIhm6gNKthLw1VR2qSOn73m80=; b=Sr4DFBboDyhfkgw/eWEOqIaRXSF7I6GXBbRxpCYTIRKz+GXe715CeKlmSJ11MjVscG vuSrCWMv+6KiJ2aICRfMPTXw1RcjlwxI8jHBJF9+h51wJYPGnLxaJQveapazqIe04ERB V3aVj7jQQA98ldur7YiZT041ETGACkZDeMqQw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0ayiDrZA6aBx9vXHSLgIhm6gNKthLw1VR2qSOn73m80=; b=g1okO3ulTJTj7jERs9kWB9TFfi41X8BAK5KIXLbPxk20Y59lL9PXqS8Gn5QY51NQe5 tSvjgmW80BkKw3mw3uVZC7X+oY8bs6O5IBwl/VG8EHulaFC99802Td1HlBJfoE+jS6B4 C1psPlj0V6TtfSHFXOuXVfBF0dpG4o14uCReNLBfrzYIM8u616GQMdf5zqx4/u6OSUrf YMDeE5bpIWN3vl+nJySE9UEBVOHieHJqhNcBO93RLQ0PmXsZMLOExMGdU4ui9fTSUkw7 D2GpdDyvjp82nHtqENnGUj5QKN/c1pVFAy5bCupEqFlIh0xjYFe2Ph+ktRykQaf1m6Rs mZQA== X-Gm-Message-State: AGRZ1gIfetuH/51a9qT+XiFWw22CnUA9HC8jYaGo1f/N8lnxR5pUx7/9 qp0tGLwi74aEVll+FYM6fryr5yWw5W8= X-Google-Smtp-Source: AJdET5caI3kG2YaK2gwL7BxUD4Dvd4jIAUWKMRMTC7fQNuXu7FbyLottjBDjklTJtQFx8bkv+mi0Qw== X-Received: by 2002:a1c:174c:: with SMTP id 73-v6mr739556wmx.105.1541166078886; Fri, 02 Nov 2018 06:41:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 13:41:09 +0000 Message-Id: <20181102134112.26370-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181102134112.26370-1-richard.henderson@linaro.org> References: <20181102134112.26370-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 1/4] target/arm: Move id_aa64mmfr* to ARMISARegisters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At the same time, define the fields for these registers, and use those defines in arm_pamax(). Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 22 ++++++++++++++++++++-- target/arm/internals.h | 3 ++- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 4 ++-- 4 files changed, 27 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8e6779936e..2ce5e80dfc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -815,6 +815,8 @@ struct ARMCPU { uint64_t id_aa64isar1; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; + uint64_t id_aa64mmfr0; + uint64_t id_aa64mmfr1; } isar; uint32_t midr; uint32_t revidr; @@ -836,8 +838,6 @@ struct ARMCPU { uint64_t id_aa64dfr1; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint64_t id_aa64mmfr0; - uint64_t id_aa64mmfr1; uint32_t dbgdidr; uint32_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ @@ -1554,6 +1554,24 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) =20 +FIELD(ID_AA64MMFR0, PARange, 0, 4) +FIELD(ID_AA64MMFR0, ASIDBits, 4, 4) +FIELD(ID_AA64MMFR0, BigEnd, 8, 4) +FIELD(ID_AA64MMFR0, SNSMem, 12, 4) +FIELD(ID_AA64MMFR0, BigEndEL0, 16, 4) +FIELD(ID_AA64MMFR0, TGran16, 20, 4) +FIELD(ID_AA64MMFR0, TGran64, 24, 4) +FIELD(ID_AA64MMFR0, TGran4, 28, 4) + +FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) +FIELD(ID_AA64MMFR1, VMIDBits, 4, 4) +FIELD(ID_AA64MMFR1, VH, 8, 4) +FIELD(ID_AA64MMFR1, HPDS, 12, 4) +FIELD(ID_AA64MMFR1, LO, 16, 4) +FIELD(ID_AA64MMFR1, PAN, 20, 4) +FIELD(ID_AA64MMFR1, SpecSEI, 24, 4) +FIELD(ID_AA64MMFR1, XNX, 28, 4) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c2bb2deeb..bf844abc47 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -213,7 +213,8 @@ static inline unsigned int arm_pamax(ARMCPU *cpu) [4] =3D 44, [5] =3D 48, }; - unsigned int parange =3D extract32(cpu->id_aa64mmfr0, 0, 4); + unsigned int parange =3D + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARange); =20 /* id_aa64mmfr0 is a read-only register so values outside of the * supported mappings can be considered an implementation error. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 873f059bf2..0babe483ac 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -141,7 +141,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->pmceid0 =3D 0x00000000; cpu->pmceid1 =3D 0x00000000; cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->id_aa64mmfr0 =3D 0x00001124; + cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->dbgdidr =3D 0x3516d000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ @@ -195,7 +195,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ + cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ cpu->dbgdidr =3D 0x3516d000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ @@ -249,7 +249,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->pmceid0 =3D 0x00000000; cpu->pmceid1 =3D 0x00000000; cpu->isar.id_aa64isar0 =3D 0x00011120; - cpu->id_aa64mmfr0 =3D 0x00001124; + cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->dbgdidr =3D 0x3516d000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ea95b0815..70376764cb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5228,11 +5228,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "ID_AA64MMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64mmfr0 }, + .resetvalue =3D cpu->isar.id_aa64mmfr0 }, { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64mmfr1 }, + .resetvalue =3D cpu->isar.id_aa64mmfr1 }, { .name =3D "ID_AA64MMFR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, --=20 2.17.2 From nobody Sun Apr 28 21:06:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541166216420652.9848668374327; Fri, 2 Nov 2018 06:43:36 -0700 (PDT) Received: from localhost ([::1]:51765 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIZjW-0000Ez-Tz for importer@patchew.org; Fri, 02 Nov 2018 09:43:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60713) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIZhl-00078v-AL for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gIZhj-0007Mc-Dp for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:41 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:37029) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gIZhj-0007BJ-48 for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:39 -0400 Received: by mail-wm1-x342.google.com with SMTP id p2-v6so1946947wmc.2 for ; Fri, 02 Nov 2018 06:41:21 -0700 (PDT) Received: from cloudburst.Home ([2a02:c7f:504f:6300:a3de:88d8:75ae:bf4c]) by smtp.gmail.com with ESMTPSA id e10-v6sm1629686wrp.56.2018.11.02.06.41.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 02 Nov 2018 06:41:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ibpO8aAfuGlV+RemFfOG8a6k0Psov4g1AaQlMHudcgg=; b=dYYanNypVMR8K+kdz6rgbEYv+mhyF/Nm0Yq/babvhX6H3pulHbuR1kbYYBgCMlKmEu cLa3RoyHPum81BJEnwG8cmWudlH+CclPrYnD5rJ5tKa3v5HXTGkYRfMqfu6D6k9L/14I Wv9+zx2hLL5FqsM3zE2CjwYp2e3E96fCIGPEY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ibpO8aAfuGlV+RemFfOG8a6k0Psov4g1AaQlMHudcgg=; b=Rue4IkxptEic4hQXr7q/hpx5Zk3WqRRF6zvzyamWEBKXDW+D9k6ReT3krFyIulqMEk pNTTl+WeOF13LmKHf3V+QPjJBdCKMhQ+fXeORmiV2CRsWgXP9ev5FdgUjupRaby6iSxt U29iDBpB6+nVrpdj+ehKaeGRzmTNlk9ppMsJ4CgLglvgqN8STL0V0nXWgWdyK+K4VAxF ISm2zsKxXpD1ivG2EREopMsdh1GeIzGPvhT+KLWHXfTI/24Jr5B96l/9fGcGkKC08HRa prZuPeRZ3ZPaSdyBvqHFOFfB6LNv4OQYFRFfvyvw4bGADXL24LV7XHXukas1/DLW+leH K8fw== X-Gm-Message-State: AGRZ1gJnyKOjNSXkBiV2g9IoM+xIGtmk1gHFQ6GKps9p0eWkIBG1PtlY t0focg4SFNhT1qGfMOIiTKXr7TzBVYw= X-Google-Smtp-Source: AJdET5fm5J2DugVu0DZfqXUWnE2ijaps9UQXnd0WKPo91h3RRtIEZqh0dmQiw1ks+lNU/AIwOgCrJA== X-Received: by 2002:a1c:8d2:: with SMTP id 201-v6mr13439wmi.132.1541166079880; Fri, 02 Nov 2018 06:41:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 13:41:10 +0000 Message-Id: <20181102134112.26370-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181102134112.26370-1-richard.henderson@linaro.org> References: <20181102134112.26370-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH for-4.0 2/4] target/arm: Implement the ARMv8.1-LOR extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Provide a trivial implementation with zero limited ordering regions, which causes the LDLAR and STLLR instructions to devolve into the LDAR and STLR instructions from the base ARMv8.0 instruction set. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 4 ++++ target/arm/helper.c | 26 ++++++++++++++++++++++++++ target/arm/translate-a64.c | 12 ++++++++++++ 4 files changed, 47 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2ce5e80dfc..f12a6afddc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3278,6 +3278,11 @@ static inline bool isar_feature_aa64_atomics(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) !=3D 0; } =20 +static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR1, LO) !=3D 0; +} + static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0babe483ac..aac6283018 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -324,6 +324,10 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); cpu->isar.id_aa64pfr0 =3D t; =20 + t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); + cpu->isar.id_aa64mmfr1 =3D t; + /* Replicate the same data to the 32-bit id registers. */ u =3D cpu->isar.id_isar5; u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 70376764cb..758ddac5e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5714,6 +5714,32 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &sctlr); } =20 + if (cpu_isar_feature(aa64_lor, cpu)) { + /* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ + static const ARMCPRegInfo lor_reginfo[] =3D { + { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D = 0 }, + { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D = 0 }, + { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D = 0 }, + { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D = 0 }, + { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D= 7, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D = 0 }, + }; + define_arm_cp_regs(cpu, lor_reginfo); + } + if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 88195ab949..2307a18d5a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2290,6 +2290,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) } return; =20 + case 0x8: /* STLLR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* StoreLORelease is the same as Store-Release for QEMU. */ + /* fallthru */ case 0x9: /* STLR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn =3D=3D 31) { @@ -2301,6 +2307,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; =20 + case 0xc: /* LDLAR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ + /* fallthru */ case 0xd: /* LDAR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn =3D=3D 31) { --=20 2.17.2 From nobody Sun Apr 28 21:06:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541166214686827.2909816775865; Fri, 2 Nov 2018 06:43:34 -0700 (PDT) Received: from localhost ([::1]:51764 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIZjU-0000Dw-PU for importer@patchew.org; Fri, 02 Nov 2018 09:43:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60787) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIZhp-0007C5-AD for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gIZhn-0007PG-9H for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:45 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:54611) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gIZhl-0007Bp-Nh for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:43 -0400 Received: by mail-wm1-x343.google.com with SMTP id r63-v6so2031566wma.4 for ; Fri, 02 Nov 2018 06:41:22 -0700 (PDT) Received: from cloudburst.Home ([2a02:c7f:504f:6300:a3de:88d8:75ae:bf4c]) by smtp.gmail.com with ESMTPSA id e10-v6sm1629686wrp.56.2018.11.02.06.41.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 02 Nov 2018 06:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1B2JyR0YGxP1NV0gAS3M6j7e9uwlDrw4cyLBftZ2h8s=; b=BsXSzu/TCqyUrFOudF+KfPO8wDcm2OS+VLaS4ozVfEIBhWsQHrIsGF209upekhHqgn iuf3Ej+3M3pMT7T5ntSgzVRtl1vC2GSzF4hqYqzaB+pTeI++XNrqUh6o8uBZ69sid7jW WzuroYQ71SLo9JJ5kqaOyk+R9mwpakm1KZkp0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1B2JyR0YGxP1NV0gAS3M6j7e9uwlDrw4cyLBftZ2h8s=; b=VynqwZZ8qI2pV4/5ijP/061tRseUZsszPIZmgO182xgO/ev0gfHShjevU/HJjoz4hG j2mMw0VmNZvURQflj221BiXuLVTYm3Wl4lez5Fo8Ie8cTll8q+0SwSlwHXEgGZ/MhP+E lTTT1gQf8L+WHAOqzv4yf5IEUzhkQn9tPTILrDL7+SA0qR9zHLibR7Np9NpRF061W4iR 239SQKPSrjca9dwv3rJae079tZaz2XxQAHTEdQBpdT0vB6QtX2pfJwc5V7fDXFGhRgag oaImb1Zlf53pYuRq+jOlJAdzPVlUWoxStKBnb0nUhKnlBYm5M/716j8ckdGdKpZ96Xmm dFGQ== X-Gm-Message-State: AGRZ1gLdFKLGyDmBHOVHztw+ccqz80TOUVuBHRxQrt+beZDaglTgRo3Z Wht6rgwHXPVN/ArAXbcOApzufBxM52w= X-Google-Smtp-Source: AJdET5dUNluIMIv8hhTU5vgTvvP9EIfCubk1KcW85lf41GT9m/GCZN2vHtxP2Z3y8wXwS0sXApwSQw== X-Received: by 2002:a1c:c016:: with SMTP id q22-v6mr739940wmf.151.1541166080841; Fri, 02 Nov 2018 06:41:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 13:41:11 +0000 Message-Id: <20181102134112.26370-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181102134112.26370-1-richard.henderson@linaro.org> References: <20181102134112.26370-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH for-4.0 3/4] target/arm: Implement the ARMv8.1-HPD extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply interpret the bits as if ARMv8.1-HPD is present without checking. We will need a slightly different check for hpd for aarch32. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 1 + target/arm/helper.c | 29 +++++++++++++++++++++-------- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index aac6283018..1d57be0c91 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -325,6 +325,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); cpu->isar.id_aa64mmfr1 =3D t; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 758ddac5e9..312d3e6f02 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9682,6 +9682,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, bool ttbr1_valid =3D true; uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); + bool hpd =3D false; =20 /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -9796,6 +9797,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, if (tg =3D=3D 2) { /* 16KB pages */ stride =3D 11; } + if (aarch64) { + if (el > 1) { + hpd =3D extract64(tcr->raw_tcr, 24, 1); + } else { + hpd =3D extract64(tcr->raw_tcr, 41, 1); + } + } } else { /* We should only be here if TTBR1 is valid */ assert(ttbr1_valid); @@ -9811,6 +9819,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, if (tg =3D=3D 1) { /* 16KB pages */ stride =3D 11; } + if (aarch64) { + hpd =3D extract64(tcr->raw_tcr, 42, 1); + } } =20 /* Here we should have set up all the parameters for the translation: @@ -9904,7 +9915,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, targ= et_ulong address, descaddr =3D descriptor & descaddrmask; =20 if ((descriptor & 2) && (level < 3)) { - /* Table entry. The top five bits are attributes which may + /* Table entry. The top five bits are attributes which may * propagate down through lower levels of the table (and * which are all arranged so that 0 means "no effect", so * we can gather them up by ORing in the bits at each level). @@ -9928,14 +9939,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, /* Stage 2 table descriptors do not include any attribute fiel= ds */ break; } - /* Merge in attributes from table descriptors */ - attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ - attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APTable[1] =3D> AP= [2] */ - /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D= =3D 1 - * means "force PL1 access only", which means forcing AP[1] to 0. + /* + * Merge in attributes from table descriptors, if the + * Hierarchical Permission Disable bit is not set. */ - if (extract32(tableattrs, 2, 1)) { - attrs &=3D ~(1 << 4); + if (!hpd) { + attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + /* !APTable[0] =3D> AP[1]. */ + attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); + /* APTable[1] =3D> AP[2] */ + attrs |=3D extract32(tableattrs, 3, 1) << 5; } attrs |=3D nstable << 3; /* NS */ break; --=20 2.17.2 From nobody Sun Apr 28 21:06:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541166214642212.4328852240062; Fri, 2 Nov 2018 06:43:34 -0700 (PDT) Received: from localhost ([::1]:51763 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIZjQ-0000AY-Nk for importer@patchew.org; Fri, 02 Nov 2018 09:43:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60712) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIZhl-00078u-AI for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gIZhj-0007MM-A0 for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:41 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:44552) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gIZhh-0007CH-Ae for qemu-devel@nongnu.org; Fri, 02 Nov 2018 09:41:37 -0400 Received: by mail-wr1-x443.google.com with SMTP id d17-v6so2014235wre.11 for ; Fri, 02 Nov 2018 06:41:22 -0700 (PDT) Received: from cloudburst.Home ([2a02:c7f:504f:6300:a3de:88d8:75ae:bf4c]) by smtp.gmail.com with ESMTPSA id e10-v6sm1629686wrp.56.2018.11.02.06.41.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 02 Nov 2018 06:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZY6/7urjTRhGhj35nknHL71Em7/fMwMHdiIzfHKXepI=; b=Ia+gWIRo5PISXCS2QBrl/mV7hI9ZmkEINGeOAHVeJl6ikstds/dVFlrtguEtAvVZOQ tGCzJhlLGlXoQm+ZrqStuftZLi25Ra+uWT+DjkHL6DzKrp3pG/gSfcM8ivgCT7Tw2TZL 0V0PYmV8oCti79d883wGMVOCbPTz6vieUUniE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZY6/7urjTRhGhj35nknHL71Em7/fMwMHdiIzfHKXepI=; b=sjWYzm/hJ6Z4kpb6pWCfLQ8vJgHdRVBO9lQKaaY9TnvnANASK3optOOc9bJ2AmS8bR KpH2elBYtWV3QDbx+OwdmGfLUcXmhhSBFpURc6leSoesUPRi3dxyvWkA06REVRTKqPCj bPIV/1zbHgDqmEyDDtomxeblb0u3Y3JQV8E0vREj1Ifq63DvI5jZJy0+rk7kqICaMY5K teTCJFIPT9hC4x22Y5qHl+gWGD3KU4pMB1ummZGRV3HSqArpFLBtCu+PY9ymQdWu7C8V 1MVThVb8UnaRRyzmmAtDfH6KVZRfYXtfd13FwFAT/Mk4zUtVgm0y5Qbv3KnyTMgrG3Yf 9mTA== X-Gm-Message-State: AGRZ1gJqVUvUL2ZVxMQaLTpLVk1h9H2sXR/7vqKSWXQe+k11y7HXor6q EPMC242rGzhBW4vEqG0/+IY4ZwieeCM= X-Google-Smtp-Source: AJdET5cuAOFAUvy4UK0Po/EU58qxAjYKN/yPscPz2GhJy9G9YXXhm5yO7mqNki2b1lqAHdYZrhZO8Q== X-Received: by 2002:a5d:4306:: with SMTP id h6-v6mr10823361wrq.189.1541166081721; Fri, 02 Nov 2018 06:41:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 2 Nov 2018 13:41:12 +0000 Message-Id: <20181102134112.26370-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181102134112.26370-1-richard.henderson@linaro.org> References: <20181102134112.26370-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.0 4/4] target/arm: Implement the ARMv8.2-AA32HPD extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The bulk of the work here, beyond base HPD, is defining the TTBCR2 register. In addition we must check TTBCR.T2E, which is not present (RES0) for AArch6= 4. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 8 ++++++++ target/arm/cpu.c | 4 ++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++-------- 3 files changed, 41 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f12a6afddc..a253cdebde 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1517,6 +1517,14 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) =20 +FIELD(ID_MMFR4, SPECSEI, 0, 4) +FIELD(ID_MMFR4, AC2, 4, 4) +FIELD(ID_MMFR4, XNX, 8, 4) +FIELD(ID_MMFR4, CNP, 12, 4) +FIELD(ID_MMFR4, HPDS, 16, 4) +FIELD(ID_MMFR4, LSM, 20, 4) +FIELD(ID_MMFR4, CCIDX, 24, 4) + FIELD(ID_AA64ISAR0, AES, 4, 4) FIELD(ID_AA64ISAR0, SHA1, 8, 4) FIELD(ID_AA64ISAR0, SHA2, 12, 4) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8f16e96b6c..3fd85f21c5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1856,6 +1856,10 @@ static void arm_max_initfn(Object *obj) t =3D cpu->isar.id_isar6; t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); cpu->isar.id_isar6 =3D t; + + t =3D cpu->id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + cpu->id_mmfr4 =3D t; } #endif } diff --git a/target/arm/helper.c b/target/arm/helper.c index 312d3e6f02..85d3f4ad89 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2722,6 +2722,7 @@ static void vmsa_ttbcr_write(CPUARMState *env, const = ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu =3D arm_env_get_cpu(env); + TCR *tcr =3D raw_ptr(env, ri); =20 if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID @@ -2729,6 +2730,8 @@ static void vmsa_ttbcr_write(CPUARMState *env, const = ARMCPRegInfo *ri, */ tlb_flush(CPU(cpu)); } + /* Preserve the high half of TCR_EL1, set via TTBCR2. */ + value =3D deposit64(tcr->raw_tcr, 0, 32, value); vmsa_ttbcr_raw_write(env, ri, value); } =20 @@ -2831,6 +2834,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing + * qemu tlbs nor adjusting cached masks. + */ +static const ARMCPRegInfo ttbcr2_reginfo =3D { + .name =3D "TTBCR2", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .bank_fieldoffsets =3D { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), + offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, +}; + static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5454,6 +5467,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } else { define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); + /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ + if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) !=3D 0) { + define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); + } } if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); @@ -9797,12 +9814,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, if (tg =3D=3D 2) { /* 16KB pages */ stride =3D 11; } - if (aarch64) { - if (el > 1) { - hpd =3D extract64(tcr->raw_tcr, 24, 1); - } else { - hpd =3D extract64(tcr->raw_tcr, 41, 1); - } + if (aarch64 && el > 1) { + hpd =3D extract64(tcr->raw_tcr, 24, 1); + } else { + hpd =3D extract64(tcr->raw_tcr, 41, 1); + } + if (!aarch64) { + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &=3D extract64(tcr->raw_tcr, 6, 1); } } else { /* We should only be here if TTBR1 is valid */ @@ -9819,8 +9838,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, tar= get_ulong address, if (tg =3D=3D 1) { /* 16KB pages */ stride =3D 11; } - if (aarch64) { - hpd =3D extract64(tcr->raw_tcr, 42, 1); + hpd =3D extract64(tcr->raw_tcr, 42, 1); + if (!aarch64) { + /* For aarch32, hpd1 is not enabled without t2e as well. */ + hpd &=3D extract64(tcr->raw_tcr, 6, 1); } } =20 --=20 2.17.2