From nobody Sat May 4 18:39:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541094336963258.8159094356266; Thu, 1 Nov 2018 10:45:36 -0700 (PDT) Received: from localhost ([::1]:43299 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIH2F-0004fG-P6 for importer@patchew.org; Thu, 01 Nov 2018 13:45:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42267) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIGwT-0007lM-7T for qemu-devel@nongnu.org; Thu, 01 Nov 2018 13:39:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gIGwH-0004H0-K6 for qemu-devel@nongnu.org; Thu, 01 Nov 2018 13:39:33 -0400 Received: from mout.kundenserver.de ([217.72.192.73]:51917) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gIGw9-0004Cb-B2 for qemu-devel@nongnu.org; Thu, 01 Nov 2018 13:39:20 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue106 [212.227.15.183]) with ESMTPSA (Nemesis) id 1M5xDJ-1gAowa3x19-007SI7; Thu, 01 Nov 2018 18:39:00 +0100 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue106 [212.227.15.183]) with ESMTPSA (Nemesis) id 1M5xDJ-1gAowa3x19-007SI7; Thu, 01 Nov 2018 18:39:00 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 1 Nov 2018 18:38:52 +0100 Message-Id: <20181101173852.27257-1-laurent@vivier.eu> X-Mailer: git-send-email 2.17.2 X-Provags-ID: V03:K1:FWq34v5Hjs3RP6NApx1Hj/3PzInz9HxVLlnV17GRA97+ngP2TWk pJQaKQfBq9ACQqSaWCHgy6RktSEeQRshAX3jUktP5ma/RbQKc2yutaVSKtuuh0pT/iAj2VO Yl2Sv7FcicVaFxEHfvw8yvhTtctXqydsWaLVujCuCOQ+tJguGUKT88eu8Oec6ohZ+63Dlj0 HjWR8mJN74VasBeistq/g== X-UI-Out-Filterresults: notjunk:1;V01:K0:mslYlNMGtUI=:1kIcMzzyFxnTs1X0+tkv0w wwaRLNkMB0NTGDj15xY2YS7zaQHKu5C0rDclYXZpGqNrWY7yj2ILcFbfbwqtTNmj3kmwdlHc3 ufo35I6ZI/znm4kHJGkekU34EaIIWZVDClesCnzQMet5Toj0zR7Kpc9znQJ+3J4g83ehaN6r2 ybNEjG97hlB1HkvsCigiPcawZHrVrdAwyT9sdNAxEki6/0Dh4G6Ijac2pLdeLOu181+tJQbQ5 HBT/rAoZ677prnq8QR4/UKGDFil6ZhYwj3S3rD5pKeBCxpYKmLarfgDZo1zp89ZjgQhnntzKc t4p71+hcWxYgpamO+r2Bq3sX06gpdZJvFIyn5o7CA6xlaImV6rj9W+Ig8SrZfkiFJVIMz2brd /QjJVSmWe1VZz/Yh8hMdOzFZaxpSmPS155RwnvG2Bp8n6FAMd9Xa98AzJGxQUU+D9jysI+Xy/ o8vQ5dNdzVIk/UbE53IgsanyVm5pJQZLRUqUZIL4abeG3W301Af0AmQJ0NKDG1QqwQZicmDM8 hu1IA51/scbLW3t+Q1ltfIXZhY16QjBRPc7hz8L2HoO2rYPCVI3gHYYNfwwfJ3qXm8Shx9dJf OIkbTSQQsbJyvSZcdwhvCR0pUSULoOHsyzIaIoP+Xp+Qgr7q1TFmu+UrOuH65HQwnp9Z4rJzz D4ufdeJao8RKCQx+VIIa6cQRbiPY1dt4ja+ELlAnvT1s9kVjnK0wWsQGdCp3JKMQd9Z4= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.72.192.73 Subject: [Qemu-devel] [PATCH] softfloat: don't execute ppc64 ISA 3.0B instruction if it is not supported X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Laurent Vivier , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" commit 27ae5109a2 has introduced an assembly instruction only supported by ISA 3.0B and it fails to execute on previous versions of the POWER CPU (like PowerPC G5). This patch fixes that by checking the ISA level, and falls back to the default C function if the instruction is not supported. Fixes: 27ae5109a2ba8b6b679cce3e03e16570a34390a0 (softfloat: Specialize udiv_qrnnd for ppc64) Signed-off-by: Laurent Vivier --- include/fpu/softfloat-macros.h | 39 ++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index c86687fa5e..fe98b33df9 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -78,6 +78,9 @@ this code that are retained. /* Portions of this work are licensed under the terms of the GNU GPL, * version 2 or later. See the COPYING file in the top-level directory. */ +#if defined(_ARCH_PPC64) +extern bool have_isa_3_00; +#endif =20 /*------------------------------------------------------------------------= ---- | Shifts `a' right by the number of bits given in `count'. If any nonzero @@ -647,25 +650,29 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64= _t n1, asm("dlgr %0, %1" : "+r"(n) : "r"(d)); *r =3D n >> 64; return n; -#elif defined(_ARCH_PPC64) - /* From Power ISA 3.0B, programming note for divdeu. */ - uint64_t q1, q2, Q, r1, r2, R; - asm("divdeu %0,%2,%4; divdu %1,%3,%4" - : "=3D&r"(q1), "=3Dr"(q2) - : "r"(n1), "r"(n0), "r"(d)); - r1 =3D -(q1 * d); /* low part of (n1<<64) - (q1 * d) */ - r2 =3D n0 - (q2 * d); - Q =3D q1 + q2; - R =3D r1 + r2; - if (R >=3D d || R < r2) { /* overflow implies R > d */ - Q +=3D 1; - R -=3D d; - } - *r =3D R; - return Q; #else uint64_t d0, d1, q0, q1, r1, r0, m; =20 +#if defined(_ARCH_PPC64) + if (have_isa_3_00) { + /* From Power ISA 3.0B, programming note for divdeu. */ + uint64_t q1, q2, Q, r1, r2, R; + asm("divdeu %0,%2,%4; divdu %1,%3,%4" + : "=3D&r"(q1), "=3Dr"(q2) + : "r"(n1), "r"(n0), "r"(d)); + r1 =3D -(q1 * d); /* low part of (n1<<64) - (q1 * d) */ + r2 =3D n0 - (q2 * d); + Q =3D q1 + q2; + R =3D r1 + r2; + if (R >=3D d || R < r2) { /* overflow implies R > d */ + Q +=3D 1; + R -=3D d; + } + *r =3D R; + return Q; + } +#endif + d0 =3D (uint32_t)d; d1 =3D d >> 32; =20 --=20 2.17.2