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[79.69.241.110]) by smtp.gmail.com with ESMTPSA id u5-v6sm7580168wrm.77.2018.10.31.09.53.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Oct 2018 09:53:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bU4KtBaMq0/J1opLvJyUc1Xb5onyX/Mfcf0M+HswhT0=; b=F29H6lK+Cp/uXb23A1uHhJWIBqbdINiFRB7J01kX3ANKxvq63cmUgK5gXWxJGOBFu1 ajSUtubEjHujAcXa62oo6lCrx/Q2n3Wpr/B7SRjJAntXG6MdfhHdl9qtbbI8L0YRYro0 di3hQw0y050ayREyAyVgA8aX3o5b6tRMqlrCI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bU4KtBaMq0/J1opLvJyUc1Xb5onyX/Mfcf0M+HswhT0=; b=VBh8yTQo5l5KbUM6QlI7D8Y/nNNDYULY8m65s618ghqisUEK94tt9lX72I6/RU3OVQ SqZHKg4Gtn77YajjNvoxeZx6a0RGxaPn8p8KXGqUHU44P5Joi3Zv6Rh082zGLG9piEkD LSPbANrcXWVb2FE81fex1wfm7GnD06QMgV1M/uhsXZ5xLSAY06HpR5SiOeRflx9oZKiI 9LrLAm0huDWlOm1W9umo+QY2/YOLnfz/aW0N3cbhGXfC0Eaj7awO9ooxWFb2afRMf5u2 UHRlM3BhCDI+rta2uMo06nmCH+D8LJvnV3dQu3Jn+CzQaqG1Ij096hLETE2T6ocNyJ6h iLlQ== X-Gm-Message-State: AGRZ1gJDbxZFGeRZZh78xHkw2uH/dqaEjCKqHb3BNFci5VvX39dexUs6 f5RWveI3COgRtN8xZ4BoWHuvKjhMtG8= X-Google-Smtp-Source: AJdET5fVsgLOYv41udS8pJ0kwUieNEvXRumEjaTu1l2SoccfmfUc2iX43ZdB55vvD/+JmXMEUW2Ejw== X-Received: by 2002:a1c:bc82:: with SMTP id m124-v6mr2981302wmf.76.1541004804734; Wed, 31 Oct 2018 09:53:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 31 Oct 2018 16:53:19 +0000 Message-Id: <20181031165321.4422-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181031165321.4422-1-richard.henderson@linaro.org> References: <20181031165321.4422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 Subject: [Qemu-devel] [PULL 1/3] decodetree: Add !extern flag to argument sets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Allow argument sets to be shared between two decoders by avoiding a re-declaration error. Make sure that anonymous argument sets and anonymous formats have unique names. Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- scripts/decodetree.py | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 457cffea90..28bbd4e3c1 100755 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -63,13 +63,16 @@ # # *** Argument set syntax: # -# args_def :=3D '&' identifier ( args_elt )+ +# args_def :=3D '&' identifier ( args_elt )+ ( !extern )? # args_elt :=3D identifier # # Each args_elt defines an argument within the argument set. # Each argument set will be rendered as a C structure "arg_$name" # with each of the fields being one of the member arguments. # +# If !extern is specified, the backing structure is assumed to +# have been already declared, typically via a second decoder. +# # Argument set examples: # # ®3 ra rb rc @@ -167,6 +170,7 @@ input_file =3D '' output_file =3D None output_fd =3D None insntype =3D 'uint32_t' +decode_function =3D 'decode' =20 re_ident =3D '[a-zA-Z][a-zA-Z0-9_]*' =20 @@ -392,8 +396,9 @@ class FunctionField: =20 class Arguments: """Class representing the extracted fields of a format""" - def __init__(self, nm, flds): + def __init__(self, nm, flds, extern): self.name =3D nm + self.extern =3D extern self.fields =3D sorted(flds) =20 def __str__(self): @@ -403,10 +408,11 @@ class Arguments: return 'arg_' + self.name =20 def output_def(self): - output('typedef struct {\n') - for n in self.fields: - output(' int ', n, ';\n') - output('} ', self.struct_name(), ';\n\n') + if not self.extern: + output('typedef struct {\n') + for n in self.fields: + output(' int ', n, ';\n') + output('} ', self.struct_name(), ';\n\n') # end Arguments =20 =20 @@ -540,7 +546,11 @@ def parse_arguments(lineno, name, toks): global re_ident =20 flds =3D [] + extern =3D False for t in toks: + if re_fullmatch('!extern', t): + extern =3D True + continue if not re_fullmatch(re_ident, t): error(lineno, 'invalid argument set token "{0}"'.format(t)) if t in flds: @@ -549,7 +559,7 @@ def parse_arguments(lineno, name, toks): =20 if name in arguments: error(lineno, 'duplicate argument set', name) - arguments[name] =3D Arguments(name, flds) + arguments[name] =3D Arguments(name, flds, extern) # end parse_arguments =20 =20 @@ -573,13 +583,14 @@ def add_field_byname(lineno, flds, new_name, old_name= ): =20 def infer_argument_set(flds): global arguments + global decode_function =20 for arg in arguments.values(): if eq_fields_for_args(flds, arg.fields): return arg =20 - name =3D str(len(arguments)) - arg =3D Arguments(name, flds.keys()) + name =3D decode_function + str(len(arguments)) + arg =3D Arguments(name, flds.keys(), False) arguments[name] =3D arg return arg =20 @@ -587,6 +598,7 @@ def infer_argument_set(flds): def infer_format(arg, fieldmask, flds): global arguments global formats + global decode_function =20 const_flds =3D {} var_flds =3D {} @@ -606,7 +618,7 @@ def infer_format(arg, fieldmask, flds): continue return (fmt, const_flds) =20 - name =3D 'Fmt_' + str(len(formats)) + name =3D decode_function + '_Fmt_' + str(len(formats)) if not arg: arg =3D infer_argument_set(flds) =20 @@ -971,8 +983,8 @@ def main(): global insnwidth global insntype global insnmask + global decode_function =20 - decode_function =3D 'decode' decode_scope =3D 'static ' =20 long_opts =3D ['decode=3D', 'translate=3D', 'output=3D', 'insnwidth=3D= '] --=20 2.17.2 From nobody Fri May 3 01:29:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[79.69.241.110]) by smtp.gmail.com with ESMTPSA id u5-v6sm7580168wrm.77.2018.10.31.09.53.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Oct 2018 09:53:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=imHEofpuwkgRwrClrY4eJUN3P2u+NJaQ/+o+uQOG8Kg=; b=ieXBDzjQ8aNXzd7qFIsygRkOv0PIElQTuddrljx+IY0Wq5N8tQyBN11C49AFTSLfwf i5oMY9V3kzkrewyLbKrS/v2ooyWZoQ2mAaIub50QC3pvVLuHwbOXt89yPS+WylonUZEj +9iPFK7g7cximIZZHM9egwwGYZKGDI+BsSPUk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=imHEofpuwkgRwrClrY4eJUN3P2u+NJaQ/+o+uQOG8Kg=; b=nN1rfG34bz3UdW8pL0g/334gmzc0WLjMa4WyBjiaZKeDBIEkGjX2hC5+Rk8m/11eHU Rrc/P0OnvfQ8TvDHRM04GOtQFI0UyZ0U4oFgYW6epB5Z7HWC6h/uf0aGRUZE/H/QEY7T hpKU6yX46jrL7UKQLy+eg2StQwNx5WgvzGa7xR3Gxs0LntsJkVAHWvGOrJ4/3OPifICS BvFNzMp7A4FcHOVji4uyebw0ake7SAZfa8zpkbkQ9jYm5H2Ce7O/LDg6ue54DCrHnqnp hwtI70Cvl8TBoyaLtijoYSWD4h++0at1ID1yqZvC8cjUKw5YiOEYqyCb25Vf4tXOVB2f p1rQ== X-Gm-Message-State: AGRZ1gIo0h7ZOpE70sDAbhtiLmdycJ+QSQyBAbdTenfO4ZCiXBTSE84/ OCvQnzEZ2Y6CIpWubWKFI3S9/E9NPXg= X-Google-Smtp-Source: AJdET5erfeub7eBU94CurU7/eM4jHF/Nh/vnh9JJHi6PpHMLHzKXJmyuVFFRB165ZQgkpMyR/Cz83g== X-Received: by 2002:a1c:a342:: with SMTP id m63-v6mr3171098wme.54.1541004806121; Wed, 31 Oct 2018 09:53:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 31 Oct 2018 16:53:20 +0000 Message-Id: <20181031165321.4422-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181031165321.4422-1-richard.henderson@linaro.org> References: <20181031165321.4422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c Subject: [Qemu-devel] [PULL 2/3] decodetree: Remove "insn" argument from trans_* expanders X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This allows trans_* expanders to be shared between decoders for 32 and 16-bit insns, by not tying the expander to the size of the insn that produced it. This change requires adjusting the two existing users to match. Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 507 +++++++++++++++++------------------- target/openrisc/disas.c | 23 +- target/openrisc/translate.c | 200 +++++++------- scripts/decodetree.py | 5 +- 4 files changed, 357 insertions(+), 378 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index fe7aebdc19..b15b615ceb 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -273,12 +273,12 @@ const uint64_t pred_esz_masks[4] =3D { *** SVE Logical - Unpredicated Group */ =20 -static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a) { return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm); } =20 -static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a) { if (a->rn =3D=3D a->rm) { /* MOV */ return do_mov_z(s, a->rd, a->rn); @@ -287,12 +287,12 @@ static bool trans_ORR_zzz(DisasContext *s, arg_rrr_es= z *a, uint32_t insn) } } =20 -static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a) { return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm); } =20 -static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a) { return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); } @@ -301,32 +301,32 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_es= z *a, uint32_t insn) *** SVE Integer Arithmetic - Unpredicated Group */ =20 -static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a) { return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm); } =20 -static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a) { return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm); } =20 -static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a) { return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm= ); } =20 -static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a) { return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm= ); } =20 -static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a) { return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm= ); } =20 -static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a) { return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm= ); } @@ -369,8 +369,7 @@ static void do_sel_z(DisasContext *s, int rd, int rn, i= nt rm, int pg, int esz) } =20 #define DO_ZPZZ(NAME, name) \ -static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a, \ - uint32_t insn) \ +static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a) \ { \ static gen_helper_gvec_4 * const fns[4] =3D { = \ gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \ @@ -402,7 +401,7 @@ DO_ZPZZ(ASR, asr) DO_ZPZZ(LSR, lsr) DO_ZPZZ(LSL, lsl) =20 -static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t ins= n) +static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a) { static gen_helper_gvec_4 * const fns[4] =3D { NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d @@ -410,7 +409,7 @@ static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_e= sz *a, uint32_t insn) return do_zpzz_ool(s, a, fns[a->esz]); } =20 -static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t ins= n) +static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a) { static gen_helper_gvec_4 * const fns[4] =3D { NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d @@ -418,7 +417,7 @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_e= sz *a, uint32_t insn) return do_zpzz_ool(s, a, fns[a->esz]); } =20 -static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn) +static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a) { if (sve_access_check(s)) { do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz); @@ -448,7 +447,7 @@ static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a,= gen_helper_gvec_3 *fn) } =20 #define DO_ZPZ(NAME, name) \ -static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \ +static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ { \ static gen_helper_gvec_3 * const fns[4] =3D { \ gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ @@ -465,7 +464,7 @@ DO_ZPZ(NOT_zpz, not_zpz) DO_ZPZ(ABS, abs) DO_ZPZ(NEG, neg) =20 -static bool trans_FABS(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FABS(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { NULL, @@ -476,7 +475,7 @@ static bool trans_FABS(DisasContext *s, arg_rpr_esz *a,= uint32_t insn) return do_zpz_ool(s, a, fns[a->esz]); } =20 -static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { NULL, @@ -487,7 +486,7 @@ static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a,= uint32_t insn) return do_zpz_ool(s, a, fns[a->esz]); } =20 -static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { NULL, @@ -498,7 +497,7 @@ static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a,= uint32_t insn) return do_zpz_ool(s, a, fns[a->esz]); } =20 -static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { NULL, @@ -509,7 +508,7 @@ static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a,= uint32_t insn) return do_zpz_ool(s, a, fns[a->esz]); } =20 -static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { NULL, NULL, @@ -519,7 +518,7 @@ static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a,= uint32_t insn) return do_zpz_ool(s, a, fns[a->esz]); } =20 -static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { NULL, NULL, @@ -529,12 +528,12 @@ static bool trans_UXTH(DisasContext *s, arg_rpr_esz *= a, uint32_t insn) return do_zpz_ool(s, a, fns[a->esz]); } =20 -static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ool(s, a, a->esz =3D=3D 3 ? gen_helper_sve_sxtw_d : NULL= ); } =20 -static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ool(s, a, a->esz =3D=3D 3 ? gen_helper_sve_uxtw_d : NULL= ); } @@ -579,7 +578,7 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, } =20 #define DO_VPZ(NAME, name) \ -static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \ +static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ { \ static gen_helper_gvec_reduc * const fns[4] =3D { = \ gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ @@ -598,7 +597,7 @@ DO_VPZ(UMAXV, umaxv) DO_VPZ(SMINV, sminv) DO_VPZ(UMINV, uminv) =20 -static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_reduc * const fns[4] =3D { gen_helper_sve_saddv_b, gen_helper_sve_saddv_h, @@ -659,7 +658,7 @@ static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *= a, return true; } =20 -static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h, @@ -675,7 +674,7 @@ static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_es= z *a, uint32_t insn) return do_zpzi_ool(s, a, fns[a->esz]); } =20 -static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h, @@ -693,7 +692,7 @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_es= z *a, uint32_t insn) } } =20 -static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h, @@ -711,7 +710,7 @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_es= z *a, uint32_t insn) } } =20 -static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { gen_helper_sve_asrd_b, gen_helper_sve_asrd_h, @@ -734,8 +733,7 @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a= , uint32_t insn) */ =20 #define DO_ZPZW(NAME, name) \ -static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a, \ - uint32_t insn) \ +static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a) \ { \ static gen_helper_gvec_4 * const fns[3] =3D { = \ gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \ @@ -784,17 +782,17 @@ static bool do_shift_imm(DisasContext *s, arg_rri_esz= *a, bool asr, return true; } =20 -static bool trans_ASR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_ASR_zzi(DisasContext *s, arg_rri_esz *a) { return do_shift_imm(s, a, true, tcg_gen_gvec_sari); } =20 -static bool trans_LSR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_LSR_zzi(DisasContext *s, arg_rri_esz *a) { return do_shift_imm(s, a, false, tcg_gen_gvec_shri); } =20 -static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a) { return do_shift_imm(s, a, false, tcg_gen_gvec_shli); } @@ -815,8 +813,7 @@ static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a,= gen_helper_gvec_3 *fn) } =20 #define DO_ZZW(NAME, name) \ -static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a, \ - uint32_t insn) \ +static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \ { \ static gen_helper_gvec_3 * const fns[4] =3D { = \ gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \ @@ -851,7 +848,7 @@ static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz= *a, } =20 #define DO_ZPZZZ(NAME, name) \ -static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a, uint32_t insn)= \ +static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \ { \ static gen_helper_gvec_5 * const fns[4] =3D { \ gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ @@ -900,7 +897,7 @@ static void do_index(DisasContext *s, int esz, int rd, tcg_temp_free_i32(desc); } =20 -static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a, uint32_t insn) +static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a) { if (sve_access_check(s)) { TCGv_i64 start =3D tcg_const_i64(a->imm1); @@ -912,7 +909,7 @@ static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_i= i *a, uint32_t insn) return true; } =20 -static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a, uint32_t insn) +static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a) { if (sve_access_check(s)) { TCGv_i64 start =3D tcg_const_i64(a->imm); @@ -923,7 +920,7 @@ static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_i= r *a, uint32_t insn) return true; } =20 -static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a, uint32_t insn) +static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a) { if (sve_access_check(s)) { TCGv_i64 start =3D cpu_reg(s, a->rn); @@ -934,7 +931,7 @@ static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_r= i *a, uint32_t insn) return true; } =20 -static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a, uint32_t insn) +static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a) { if (sve_access_check(s)) { TCGv_i64 start =3D cpu_reg(s, a->rn); @@ -948,7 +945,7 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_r= r *a, uint32_t insn) *** SVE Stack Allocation Group */ =20 -static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a, uint32_t insn) +static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) { TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); @@ -956,7 +953,7 @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a, = uint32_t insn) return true; } =20 -static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a, uint32_t insn) +static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); @@ -964,7 +961,7 @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a, = uint32_t insn) return true; } =20 -static bool trans_RDVL(DisasContext *s, arg_RDVL *a, uint32_t insn) +static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { TCGv_i64 reg =3D cpu_reg(s, a->rd); tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); @@ -987,22 +984,22 @@ static bool do_adr(DisasContext *s, arg_rrri *a, gen_= helper_gvec_3 *fn) return true; } =20 -static bool trans_ADR_p32(DisasContext *s, arg_rrri *a, uint32_t insn) +static bool trans_ADR_p32(DisasContext *s, arg_rrri *a) { return do_adr(s, a, gen_helper_sve_adr_p32); } =20 -static bool trans_ADR_p64(DisasContext *s, arg_rrri *a, uint32_t insn) +static bool trans_ADR_p64(DisasContext *s, arg_rrri *a) { return do_adr(s, a, gen_helper_sve_adr_p64); } =20 -static bool trans_ADR_s32(DisasContext *s, arg_rrri *a, uint32_t insn) +static bool trans_ADR_s32(DisasContext *s, arg_rrri *a) { return do_adr(s, a, gen_helper_sve_adr_s32); } =20 -static bool trans_ADR_u32(DisasContext *s, arg_rrri *a, uint32_t insn) +static bool trans_ADR_u32(DisasContext *s, arg_rrri *a) { return do_adr(s, a, gen_helper_sve_adr_u32); } @@ -1011,7 +1008,7 @@ static bool trans_ADR_u32(DisasContext *s, arg_rrri *= a, uint32_t insn) *** SVE Integer Misc - Unpredicated Group */ =20 -static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a, uint32_t insn) +static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a) { static gen_helper_gvec_2 * const fns[4] =3D { NULL, @@ -1031,7 +1028,7 @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *= a, uint32_t insn) return true; } =20 -static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { NULL, @@ -1120,7 +1117,7 @@ static void gen_and_pg_vec(unsigned vece, TCGv_vec pd= , TCGv_vec pn, tcg_gen_and_vec(vece, pd, pd, pg); } =20 -static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a) { static const GVecGen4 op =3D { .fni8 =3D gen_and_pg_i64, @@ -1156,7 +1153,7 @@ static void gen_bic_pg_vec(unsigned vece, TCGv_vec pd= , TCGv_vec pn, tcg_gen_and_vec(vece, pd, pd, pg); } =20 -static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a) { static const GVecGen4 op =3D { .fni8 =3D gen_bic_pg_i64, @@ -1186,7 +1183,7 @@ static void gen_eor_pg_vec(unsigned vece, TCGv_vec pd= , TCGv_vec pn, tcg_gen_and_vec(vece, pd, pd, pg); } =20 -static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a) { static const GVecGen4 op =3D { .fni8 =3D gen_eor_pg_i64, @@ -1216,7 +1213,7 @@ static void gen_sel_pg_vec(unsigned vece, TCGv_vec pd= , TCGv_vec pn, tcg_gen_or_vec(vece, pd, pn, pm); } =20 -static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a) { static const GVecGen4 op =3D { .fni8 =3D gen_sel_pg_i64, @@ -1244,7 +1241,7 @@ static void gen_orr_pg_vec(unsigned vece, TCGv_vec pd= , TCGv_vec pn, tcg_gen_and_vec(vece, pd, pd, pg); } =20 -static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a) { static const GVecGen4 op =3D { .fni8 =3D gen_orr_pg_i64, @@ -1274,7 +1271,7 @@ static void gen_orn_pg_vec(unsigned vece, TCGv_vec pd= , TCGv_vec pn, tcg_gen_and_vec(vece, pd, pd, pg); } =20 -static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a) { static const GVecGen4 op =3D { .fni8 =3D gen_orn_pg_i64, @@ -1302,7 +1299,7 @@ static void gen_nor_pg_vec(unsigned vece, TCGv_vec pd= , TCGv_vec pn, tcg_gen_andc_vec(vece, pd, pg, pd); } =20 -static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a) { static const GVecGen4 op =3D { .fni8 =3D gen_nor_pg_i64, @@ -1330,7 +1327,7 @@ static void gen_nand_pg_vec(unsigned vece, TCGv_vec p= d, TCGv_vec pn, tcg_gen_andc_vec(vece, pd, pg, pd); } =20 -static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) +static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a) { static const GVecGen4 op =3D { .fni8 =3D gen_nand_pg_i64, @@ -1349,7 +1346,7 @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr= _s *a, uint32_t insn) *** SVE Predicate Misc Group */ =20 -static bool trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn) +static bool trans_PTEST(DisasContext *s, arg_PTEST *a) { if (sve_access_check(s)) { int nofs =3D pred_full_reg_offset(s, a->rn); @@ -1491,24 +1488,24 @@ static bool do_predset(DisasContext *s, int esz, in= t rd, int pat, bool setflag) return true; } =20 -static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a, uint32_t insn) +static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a) { return do_predset(s, a->esz, a->rd, a->pat, a->s); } =20 -static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a, uint32_t insn) +static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a) { /* Note pat =3D=3D 31 is #all, to set all elements. */ return do_predset(s, 0, FFR_PRED_NUM, 31, false); } =20 -static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a, uint32_t insn) +static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a) { /* Note pat =3D=3D 32 is #unimp, to set no elements. */ return do_predset(s, 0, a->rd, 32, false); } =20 -static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a, uint32_t insn) +static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a) { /* The path through do_pppp_flags is complicated enough to want to avo= id * duplication. Frob the arguments into the form of a predicated AND. @@ -1517,15 +1514,15 @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFF= R_p *a, uint32_t insn) .rd =3D a->rd, .pg =3D a->pg, .s =3D a->s, .rn =3D FFR_PRED_NUM, .rm =3D FFR_PRED_NUM, }; - return trans_AND_pppp(s, &alt_a, insn); + return trans_AND_pppp(s, &alt_a); } =20 -static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a, uint32_t insn) +static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a) { return do_mov_p(s, a->rd, FFR_PRED_NUM); } =20 -static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a, uint32_t insn) +static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a) { return do_mov_p(s, FFR_PRED_NUM, a->rn); } @@ -1559,12 +1556,12 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr= _esz *a, return true; } =20 -static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a, uint32_t insn) +static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a) { return do_pfirst_pnext(s, a, gen_helper_sve_pfirst); } =20 -static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a, uint32_t insn) +static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a) { return do_pfirst_pnext(s, a, gen_helper_sve_pnext); } @@ -1735,7 +1732,7 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, tcg_temp_free_i32(desc); } =20 -static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a, uint32_t insn) +static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) { if (sve_access_check(s)) { unsigned fullsz =3D vec_full_reg_size(s); @@ -1745,7 +1742,7 @@ static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a= , uint32_t insn) return true; } =20 -static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a, uint32_t in= sn) +static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a) { if (sve_access_check(s)) { unsigned fullsz =3D vec_full_reg_size(s); @@ -1758,8 +1755,7 @@ static bool trans_INCDEC_r(DisasContext *s, arg_incde= c_cnt *a, uint32_t insn) return true; } =20 -static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a, - uint32_t insn) +static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a) { if (!sve_access_check(s)) { return true; @@ -1785,8 +1781,7 @@ static bool trans_SINCDEC_r_32(DisasContext *s, arg_i= ncdec_cnt *a, return true; } =20 -static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a, - uint32_t insn) +static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a) { if (!sve_access_check(s)) { return true; @@ -1805,7 +1800,7 @@ static bool trans_SINCDEC_r_64(DisasContext *s, arg_i= ncdec_cnt *a, return true; } =20 -static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a, uint32_t i= nsn) +static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a) { if (a->esz =3D=3D 0) { return false; @@ -1829,8 +1824,7 @@ static bool trans_INCDEC_v(DisasContext *s, arg_incde= c2_cnt *a, uint32_t insn) return true; } =20 -static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a, - uint32_t insn) +static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a) { if (a->esz =3D=3D 0) { return false; @@ -1872,22 +1866,22 @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *= a, GVecGen2iFn *gvec_fn) return true; } =20 -static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn) +static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a) { return do_zz_dbm(s, a, tcg_gen_gvec_andi); } =20 -static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn) +static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a) { return do_zz_dbm(s, a, tcg_gen_gvec_ori); } =20 -static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn) +static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a) { return do_zz_dbm(s, a, tcg_gen_gvec_xori); } =20 -static bool trans_DUPM(DisasContext *s, arg_DUPM *a, uint32_t insn) +static bool trans_DUPM(DisasContext *s, arg_DUPM *a) { uint64_t imm; if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), @@ -1934,7 +1928,7 @@ static void do_cpy_m(DisasContext *s, int esz, int rd= , int rn, int pg, tcg_temp_free_i32(desc); } =20 -static bool trans_FCPY(DisasContext *s, arg_FCPY *a, uint32_t insn) +static bool trans_FCPY(DisasContext *s, arg_FCPY *a) { if (a->esz =3D=3D 0) { return false; @@ -1949,9 +1943,9 @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a, = uint32_t insn) return true; } =20 -static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a, uint32_t insn) +static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a) { - if (a->esz =3D=3D 0 && extract32(insn, 13, 1)) { + if (a->esz =3D=3D 0 && extract32(s->insn, 13, 1)) { return false; } if (sve_access_check(s)) { @@ -1962,14 +1956,14 @@ static bool trans_CPY_m_i(DisasContext *s, arg_rpri= _esz *a, uint32_t insn) return true; } =20 -static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a, uint32_t insn) +static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a) { static gen_helper_gvec_2i * const fns[4] =3D { gen_helper_sve_cpy_z_b, gen_helper_sve_cpy_z_h, gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d, }; =20 - if (a->esz =3D=3D 0 && extract32(insn, 13, 1)) { + if (a->esz =3D=3D 0 && extract32(s->insn, 13, 1)) { return false; } if (sve_access_check(s)) { @@ -1987,7 +1981,7 @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_= i *a, uint32_t insn) *** SVE Permute Extract Group */ =20 -static bool trans_EXT(DisasContext *s, arg_EXT *a, uint32_t insn) +static bool trans_EXT(DisasContext *s, arg_EXT *a) { if (!sve_access_check(s)) { return true; @@ -2021,7 +2015,7 @@ static bool trans_EXT(DisasContext *s, arg_EXT *a, ui= nt32_t insn) *** SVE Permute - Unpredicated Group */ =20 -static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a, uint32_t insn) +static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a) { if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); @@ -2031,7 +2025,7 @@ static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a= , uint32_t insn) return true; } =20 -static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a, uint32_t insn) +static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a) { if ((a->imm & 0x1f) =3D=3D 0) { return false; @@ -2076,7 +2070,7 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz = *a, TCGv_i64 val) tcg_temp_free_i32(desc); } =20 -static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a) { if (sve_access_check(s)) { TCGv_i64 t =3D tcg_temp_new_i64(); @@ -2087,7 +2081,7 @@ static bool trans_INSR_f(DisasContext *s, arg_rrr_esz= *a, uint32_t insn) return true; } =20 -static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a) { if (sve_access_check(s)) { do_insr_i64(s, a, cpu_reg(s, a->rm)); @@ -2095,7 +2089,7 @@ static bool trans_INSR_r(DisasContext *s, arg_rrr_esz= *a, uint32_t insn) return true; } =20 -static bool trans_REV_v(DisasContext *s, arg_rr_esz *a, uint32_t insn) +static bool trans_REV_v(DisasContext *s, arg_rr_esz *a) { static gen_helper_gvec_2 * const fns[4] =3D { gen_helper_sve_rev_b, gen_helper_sve_rev_h, @@ -2111,7 +2105,7 @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *= a, uint32_t insn) return true; } =20 -static bool trans_TBL(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_TBL(DisasContext *s, arg_rrr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { gen_helper_sve_tbl_b, gen_helper_sve_tbl_h, @@ -2128,7 +2122,7 @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a= , uint32_t insn) return true; } =20 -static bool trans_UNPK(DisasContext *s, arg_UNPK *a, uint32_t insn) +static bool trans_UNPK(DisasContext *s, arg_UNPK *a) { static gen_helper_gvec_2 * const fns[4][2] =3D { { NULL, NULL }, @@ -2225,47 +2219,47 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_e= sz *a, bool high_odd, return true; } =20 -static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a) { return do_perm_pred3(s, a, 0, gen_helper_sve_zip_p); } =20 -static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a) { return do_perm_pred3(s, a, 1, gen_helper_sve_zip_p); } =20 -static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a) { return do_perm_pred3(s, a, 0, gen_helper_sve_uzp_p); } =20 -static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a) { return do_perm_pred3(s, a, 1, gen_helper_sve_uzp_p); } =20 -static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a) { return do_perm_pred3(s, a, 0, gen_helper_sve_trn_p); } =20 -static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a) { return do_perm_pred3(s, a, 1, gen_helper_sve_trn_p); } =20 -static bool trans_REV_p(DisasContext *s, arg_rr_esz *a, uint32_t insn) +static bool trans_REV_p(DisasContext *s, arg_rr_esz *a) { return do_perm_pred2(s, a, 0, gen_helper_sve_rev_p); } =20 -static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a, uint32_t insn) +static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a) { return do_perm_pred2(s, a, 0, gen_helper_sve_punpk_p); } =20 -static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a, uint32_t insn) +static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a) { return do_perm_pred2(s, a, 1, gen_helper_sve_punpk_p); } @@ -2305,12 +2299,12 @@ static bool do_zzz_data_ool(DisasContext *s, arg_rr= r_esz *a, int data, return true; } =20 -static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a) { return do_zip(s, a, false); } =20 -static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a) { return do_zip(s, a, true); } @@ -2320,12 +2314,12 @@ static gen_helper_gvec_3 * const uzp_fns[4] =3D { gen_helper_sve_uzp_s, gen_helper_sve_uzp_d, }; =20 -static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a) { return do_zzz_data_ool(s, a, 0, uzp_fns[a->esz]); } =20 -static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a) { return do_zzz_data_ool(s, a, 1 << a->esz, uzp_fns[a->esz]); } @@ -2335,12 +2329,12 @@ static gen_helper_gvec_3 * const trn_fns[4] =3D { gen_helper_sve_trn_s, gen_helper_sve_trn_d, }; =20 -static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a) { return do_zzz_data_ool(s, a, 0, trn_fns[a->esz]); } =20 -static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a) { return do_zzz_data_ool(s, a, 1 << a->esz, trn_fns[a->esz]); } @@ -2349,7 +2343,7 @@ static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz= *a, uint32_t insn) *** SVE Permute Vector - Predicated Group */ =20 -static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d @@ -2516,12 +2510,12 @@ static bool do_clast_vector(DisasContext *s, arg_rp= rr_esz *a, bool before) return true; } =20 -static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a, uint32_t insn) +static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a) { return do_clast_vector(s, a, false); } =20 -static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a, uint32_t insn) +static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a) { return do_clast_vector(s, a, true); } @@ -2574,12 +2568,12 @@ static bool do_clast_fp(DisasContext *s, arg_rpr_es= z *a, bool before) return true; } =20 -static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a) { return do_clast_fp(s, a, false); } =20 -static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a) { return do_clast_fp(s, a, true); } @@ -2614,12 +2608,12 @@ static bool do_clast_general(DisasContext *s, arg_r= pr_esz *a, bool before) return true; } =20 -static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a) { return do_clast_general(s, a, false); } =20 -static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a) { return do_clast_general(s, a, true); } @@ -2654,12 +2648,12 @@ static bool do_last_fp(DisasContext *s, arg_rpr_esz= *a, bool before) return true; } =20 -static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a) { return do_last_fp(s, a, false); } =20 -static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a) { return do_last_fp(s, a, true); } @@ -2675,17 +2669,17 @@ static bool do_last_general(DisasContext *s, arg_rp= r_esz *a, bool before) return true; } =20 -static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a) { return do_last_general(s, a, false); } =20 -static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a) { return do_last_general(s, a, true); } =20 -static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a) { if (sve_access_check(s)) { do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn)); @@ -2693,7 +2687,7 @@ static bool trans_CPY_m_r(DisasContext *s, arg_rpr_es= z *a, uint32_t insn) return true; } =20 -static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a) { if (sve_access_check(s)) { int ofs =3D vec_reg_offset(s, a->rn, 0, a->esz); @@ -2704,7 +2698,7 @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_es= z *a, uint32_t insn) return true; } =20 -static bool trans_REVB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_REVB(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { NULL, @@ -2715,7 +2709,7 @@ static bool trans_REVB(DisasContext *s, arg_rpr_esz *= a, uint32_t insn) return do_zpz_ool(s, a, fns[a->esz]); } =20 -static bool trans_REVH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_REVH(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { NULL, @@ -2726,12 +2720,12 @@ static bool trans_REVH(DisasContext *s, arg_rpr_esz= *a, uint32_t insn) return do_zpz_ool(s, a, fns[a->esz]); } =20 -static bool trans_REVW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_REVW(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ool(s, a, a->esz =3D=3D 3 ? gen_helper_sve_revw_d : NULL= ); } =20 -static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3 * const fns[4] =3D { gen_helper_sve_rbit_b, @@ -2742,7 +2736,7 @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *= a, uint32_t insn) return do_zpz_ool(s, a, fns[a->esz]); } =20 -static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a, uint32_t insn) +static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a) { if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); @@ -2799,8 +2793,7 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_e= sz *a, } =20 #define DO_PPZZ(NAME, name) \ -static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a, \ - uint32_t insn) \ +static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \ { \ static gen_helper_gvec_flags_4 * const fns[4] =3D { = \ gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \ @@ -2819,8 +2812,7 @@ DO_PPZZ(CMPHS, cmphs) #undef DO_PPZZ =20 #define DO_PPZW(NAME, name) \ -static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a, \ - uint32_t insn) \ +static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a) \ { \ static gen_helper_gvec_flags_4 * const fns[4] =3D { = \ gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \ @@ -2883,8 +2875,7 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_e= sz *a, } =20 #define DO_PPZI(NAME, name) \ -static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a, \ - uint32_t insn) \ +static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a) \ { \ static gen_helper_gvec_flags_3 * const fns[4] =3D { = \ gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \ @@ -2977,37 +2968,37 @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a, return true; } =20 -static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a, uint32_t insn) +static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a) { return do_brk3(s, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas); } =20 -static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a, uint32_t insn) +static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a) { return do_brk3(s, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs); } =20 -static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a, uint32_t insn) +static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a) { return do_brk2(s, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m); } =20 -static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a, uint32_t insn) +static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a) { return do_brk2(s, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m); } =20 -static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a, uint32_t insn) +static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a) { return do_brk2(s, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z); } =20 -static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a, uint32_t insn) +static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a) { return do_brk2(s, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z); } =20 -static bool trans_BRKN(DisasContext *s, arg_rpr_s *a, uint32_t insn) +static bool trans_BRKN(DisasContext *s, arg_rpr_s *a) { return do_brk2(s, a, gen_helper_sve_brkn, gen_helper_sve_brkns); } @@ -3058,7 +3049,7 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, in= t esz, int pn, int pg) } } =20 -static bool trans_CNTP(DisasContext *s, arg_CNTP *a, uint32_t insn) +static bool trans_CNTP(DisasContext *s, arg_CNTP *a) { if (sve_access_check(s)) { do_cntp(s, cpu_reg(s, a->rd), a->esz, a->rn, a->pg); @@ -3066,8 +3057,7 @@ static bool trans_CNTP(DisasContext *s, arg_CNTP *a, = uint32_t insn) return true; } =20 -static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a, - uint32_t insn) +static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a) { if (sve_access_check(s)) { TCGv_i64 reg =3D cpu_reg(s, a->rd); @@ -3084,8 +3074,7 @@ static bool trans_INCDECP_r(DisasContext *s, arg_incd= ec_pred *a, return true; } =20 -static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a, - uint32_t insn) +static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a) { if (a->esz =3D=3D 0) { return false; @@ -3102,8 +3091,7 @@ static bool trans_INCDECP_z(DisasContext *s, arg_incd= ec2_pred *a, return true; } =20 -static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a, - uint32_t insn) +static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a) { if (sve_access_check(s)) { TCGv_i64 reg =3D cpu_reg(s, a->rd); @@ -3115,8 +3103,7 @@ static bool trans_SINCDECP_r_32(DisasContext *s, arg_= incdec_pred *a, return true; } =20 -static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a, - uint32_t insn) +static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a) { if (sve_access_check(s)) { TCGv_i64 reg =3D cpu_reg(s, a->rd); @@ -3128,8 +3115,7 @@ static bool trans_SINCDECP_r_64(DisasContext *s, arg_= incdec_pred *a, return true; } =20 -static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a, - uint32_t insn) +static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a) { if (a->esz =3D=3D 0) { return false; @@ -3146,7 +3132,7 @@ static bool trans_SINCDECP_z(DisasContext *s, arg_inc= dec2_pred *a, *** SVE Integer Compare Scalars Group */ =20 -static bool trans_CTERM(DisasContext *s, arg_CTERM *a, uint32_t insn) +static bool trans_CTERM(DisasContext *s, arg_CTERM *a) { if (!sve_access_check(s)) { return true; @@ -3171,7 +3157,7 @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a= , uint32_t insn) return true; } =20 -static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn) +static bool trans_WHILE(DisasContext *s, arg_WHILE *a) { TCGv_i64 op0, op1, t0, t1, tmax; TCGv_i32 t2, t3; @@ -3260,7 +3246,7 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a= , uint32_t insn) *** SVE Integer Wide Immediate - Unpredicated Group */ =20 -static bool trans_FDUP(DisasContext *s, arg_FDUP *a, uint32_t insn) +static bool trans_FDUP(DisasContext *s, arg_FDUP *a) { if (a->esz =3D=3D 0) { return false; @@ -3279,9 +3265,9 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a, = uint32_t insn) return true; } =20 -static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a, uint32_t insn) +static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) { - if (a->esz =3D=3D 0 && extract32(insn, 13, 1)) { + if (a->esz =3D=3D 0 && extract32(s->insn, 13, 1)) { return false; } if (sve_access_check(s)) { @@ -3293,9 +3279,9 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a= , uint32_t insn) return true; } =20 -static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a) { - if (a->esz =3D=3D 0 && extract32(insn, 13, 1)) { + if (a->esz =3D=3D 0 && extract32(s->insn, 13, 1)) { return false; } if (sve_access_check(s)) { @@ -3306,13 +3292,13 @@ static bool trans_ADD_zzi(DisasContext *s, arg_rri_= esz *a, uint32_t insn) return true; } =20 -static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a) { a->imm =3D -a->imm; - return trans_ADD_zzi(s, a, insn); + return trans_ADD_zzi(s, a); } =20 -static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a) { static const GVecGen2s op[4] =3D { { .fni8 =3D tcg_gen_vec_sub8_i64, @@ -3342,7 +3328,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_e= sz *a, uint32_t insn) .scalar_first =3D true } }; =20 - if (a->esz =3D=3D 0 && extract32(insn, 13, 1)) { + if (a->esz =3D=3D 0 && extract32(s->insn, 13, 1)) { return false; } if (sve_access_check(s)) { @@ -3356,7 +3342,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_e= sz *a, uint32_t insn) return true; } =20 -static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a) { if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); @@ -3366,10 +3352,9 @@ static bool trans_MUL_zzi(DisasContext *s, arg_rri_e= sz *a, uint32_t insn) return true; } =20 -static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, uint32_t insn, - bool u, bool d) +static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d) { - if (a->esz =3D=3D 0 && extract32(insn, 13, 1)) { + if (a->esz =3D=3D 0 && extract32(s->insn, 13, 1)) { return false; } if (sve_access_check(s)) { @@ -3380,24 +3365,24 @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz= *a, uint32_t insn, return true; } =20 -static bool trans_SQADD_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_SQADD_zzi(DisasContext *s, arg_rri_esz *a) { - return do_zzi_sat(s, a, insn, false, false); + return do_zzi_sat(s, a, false, false); } =20 -static bool trans_UQADD_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_UQADD_zzi(DisasContext *s, arg_rri_esz *a) { - return do_zzi_sat(s, a, insn, true, false); + return do_zzi_sat(s, a, true, false); } =20 -static bool trans_SQSUB_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_SQSUB_zzi(DisasContext *s, arg_rri_esz *a) { - return do_zzi_sat(s, a, insn, false, true); + return do_zzi_sat(s, a, false, true); } =20 -static bool trans_UQSUB_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +static bool trans_UQSUB_zzi(DisasContext *s, arg_rri_esz *a) { - return do_zzi_sat(s, a, insn, true, true); + return do_zzi_sat(s, a, true, true); } =20 static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i= *fn) @@ -3415,8 +3400,7 @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *= a, gen_helper_gvec_2i *fn) } =20 #define DO_ZZI(NAME, name) \ -static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a, \ - uint32_t insn) \ +static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a) \ { \ static gen_helper_gvec_2i * const fns[4] =3D { \ gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \ @@ -3432,7 +3416,7 @@ DO_ZZI(UMIN, umin) =20 #undef DO_ZZI =20 -static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a, uint32_t insn) +static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a) { static gen_helper_gvec_3 * const fns[2][2] =3D { { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h }, @@ -3449,7 +3433,7 @@ static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zz= z *a, uint32_t insn) return true; } =20 -static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zzx *a, uint32_t insn) +static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zzx *a) { static gen_helper_gvec_3 * const fns[2][2] =3D { { gen_helper_gvec_sdot_idx_b, gen_helper_gvec_sdot_idx_h }, @@ -3471,7 +3455,7 @@ static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zz= x *a, uint32_t insn) *** SVE Floating Point Multiply-Add Indexed Group */ =20 -static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a, uint32_t in= sn) +static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a) { static gen_helper_gvec_4_ptr * const fns[3] =3D { gen_helper_gvec_fmla_idx_h, @@ -3497,7 +3481,7 @@ static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA= _zzxz *a, uint32_t insn) *** SVE Floating Point Multiply Indexed Group */ =20 -static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a, uint32_t insn) +static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a) { static gen_helper_gvec_3_ptr * const fns[3] =3D { gen_helper_gvec_fmul_idx_h, @@ -3552,7 +3536,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a, } =20 #define DO_VPZ(NAME, name) \ -static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \ +static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ { \ static gen_helper_fp_reduce * const fns[3] =3D { = \ gen_helper_sve_##name##_h, \ @@ -3589,7 +3573,7 @@ static void do_zz_fp(DisasContext *s, arg_rr_esz *a, = gen_helper_gvec_2_ptr *fn) tcg_temp_free_ptr(status); } =20 -static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a, uint32_t insn) +static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a) { static gen_helper_gvec_2_ptr * const fns[3] =3D { gen_helper_gvec_frecpe_h, @@ -3605,7 +3589,7 @@ static bool trans_FRECPE(DisasContext *s, arg_rr_esz = *a, uint32_t insn) return true; } =20 -static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a, uint32_t insn) +static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a) { static gen_helper_gvec_2_ptr * const fns[3] =3D { gen_helper_gvec_frsqrte_h, @@ -3639,7 +3623,7 @@ static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a, } =20 #define DO_PPZ(NAME, name) \ -static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \ +static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \ { \ static gen_helper_gvec_3_ptr * const fns[3] =3D { \ gen_helper_sve_##name##_h, \ @@ -3668,7 +3652,7 @@ DO_PPZ(FCMNE_ppz0, fcmne0) *** SVE floating-point trig multiply-add coefficient */ =20 -static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a, uint32_t insn) +static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a) { static gen_helper_gvec_3_ptr * const fns[3] =3D { gen_helper_sve_ftmad_h, @@ -3695,7 +3679,7 @@ static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a= , uint32_t insn) *** SVE Floating Point Accumulating Reduction Group */ =20 -static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a, uint32_t insn) +static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) { typedef void fadda_fn(TCGv_i64, TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); @@ -3760,7 +3744,7 @@ static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a, =20 =20 #define DO_FP3(NAME, name) \ -static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a, uint32_t insn) \ +static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \ { \ static gen_helper_gvec_3_ptr * const fns[4] =3D { \ NULL, gen_helper_gvec_##name##_h, \ @@ -3802,7 +3786,7 @@ static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz = *a, } =20 #define DO_FP3(NAME, name) \ -static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a, uint32_t insn) \ +static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \ { \ static gen_helper_gvec_4_ptr * const fns[4] =3D { \ NULL, gen_helper_sve_##name##_h, \ @@ -3862,8 +3846,7 @@ static void do_fp_imm(DisasContext *s, arg_rpri_esz *= a, uint64_t imm, } =20 #define DO_FP_IMM(NAME, name, const0, const1) \ -static bool trans_##NAME##_zpzi(DisasContext *s, arg_rpri_esz *a, \ - uint32_t insn) \ +static bool trans_##NAME##_zpzi(DisasContext *s, arg_rpri_esz *a) \ { \ static gen_helper_sve_fp2scalar * const fns[3] =3D { = \ gen_helper_sve_##name##_h, \ @@ -3919,8 +3902,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *= a, } =20 #define DO_FPCMP(NAME, name) \ -static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a, \ - uint32_t insn) \ +static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \ { \ static gen_helper_gvec_4_ptr * const fns[4] =3D { \ NULL, gen_helper_sve_##name##_h, \ @@ -3939,7 +3921,7 @@ DO_FPCMP(FACGT, facgt) =20 #undef DO_FPCMP =20 -static bool trans_FCADD(DisasContext *s, arg_FCADD *a, uint32_t insn) +static bool trans_FCADD(DisasContext *s, arg_FCADD *a) { static gen_helper_gvec_4_ptr * const fns[3] =3D { gen_helper_sve_fcadd_h, @@ -3996,7 +3978,7 @@ static bool do_fmla(DisasContext *s, arg_rprrr_esz *a= , gen_helper_sve_fmla *fn) } =20 #define DO_FMLA(NAME, name) \ -static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a, uint32_t insn)= \ +static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \ { \ static gen_helper_sve_fmla * const fns[4] =3D { \ NULL, gen_helper_sve_##name##_h, \ @@ -4012,8 +3994,7 @@ DO_FMLA(FNMLS_zpzzz, fnmls_zpzzz) =20 #undef DO_FMLA =20 -static bool trans_FCMLA_zpzzz(DisasContext *s, - arg_FCMLA_zpzzz *a, uint32_t insn) +static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a) { static gen_helper_sve_fmla * const fns[3] =3D { gen_helper_sve_fcmla_zpzzz_h, @@ -4049,7 +4030,7 @@ static bool trans_FCMLA_zpzzz(DisasContext *s, return true; } =20 -static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a, uint32_t = insn) +static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a) { static gen_helper_gvec_3_ptr * const fns[2] =3D { gen_helper_gvec_fcmlah_idx, @@ -4091,102 +4072,102 @@ static bool do_zpz_ptr(DisasContext *s, int rd, i= nt rn, int pg, return true; } =20 -static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_s= h); } =20 -static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_h= s); } =20 -static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_d= h); } =20 -static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_h= d); } =20 -static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_d= s); } =20 -static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_s= d); } =20 -static bool trans_FCVTZS_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZS_hh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_= hh); } =20 -static bool trans_FCVTZU_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZU_hh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_= hh); } =20 -static bool trans_FCVTZS_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZS_hs(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_= hs); } =20 -static bool trans_FCVTZU_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZU_hs(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_= hs); } =20 -static bool trans_FCVTZS_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZS_hd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_= hd); } =20 -static bool trans_FCVTZU_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZU_hd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_= hd); } =20 -static bool trans_FCVTZS_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZS_ss(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs= _ss); } =20 -static bool trans_FCVTZU_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZU_ss(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu= _ss); } =20 -static bool trans_FCVTZS_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZS_sd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs= _sd); } =20 -static bool trans_FCVTZU_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZU_sd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu= _sd); } =20 -static bool trans_FCVTZS_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZS_ds(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs= _ds); } =20 -static bool trans_FCVTZU_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZU_ds(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu= _ds); } =20 -static bool trans_FCVTZS_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZS_dd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs= _dd); } =20 -static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu= _dd); } @@ -4197,7 +4178,7 @@ static gen_helper_gvec_3_ptr * const frint_fns[3] =3D= { gen_helper_sve_frint_d }; =20 -static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a) { if (a->esz =3D=3D 0) { return false; @@ -4206,7 +4187,7 @@ static bool trans_FRINTI(DisasContext *s, arg_rpr_esz= *a, uint32_t insn) frint_fns[a->esz - 1]); } =20 -static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3_ptr * const fns[3] =3D { gen_helper_sve_frintx_h, @@ -4243,32 +4224,32 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_= esz *a, int mode) return true; } =20 -static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a) { return do_frint_mode(s, a, float_round_nearest_even); } =20 -static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a) { return do_frint_mode(s, a, float_round_up); } =20 -static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a) { return do_frint_mode(s, a, float_round_down); } =20 -static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a) { return do_frint_mode(s, a, float_round_to_zero); } =20 -static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a) { return do_frint_mode(s, a, float_round_ties_away); } =20 -static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3_ptr * const fns[3] =3D { gen_helper_sve_frecpx_h, @@ -4281,7 +4262,7 @@ static bool trans_FRECPX(DisasContext *s, arg_rpr_esz= *a, uint32_t insn) return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz =3D=3D MO_16, fns[a->= esz - 1]); } =20 -static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a) { static gen_helper_gvec_3_ptr * const fns[3] =3D { gen_helper_sve_fsqrt_h, @@ -4294,72 +4275,72 @@ static bool trans_FSQRT(DisasContext *s, arg_rpr_es= z *a, uint32_t insn) return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz =3D=3D MO_16, fns[a->= esz - 1]); } =20 -static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh= ); } =20 -static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_sh= ); } =20 -static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_dh= ); } =20 -static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_s= s); } =20 -static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_d= s); } =20 -static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_s= d); } =20 -static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_d= d); } =20 -static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_hh= ); } =20 -static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_sh= ); } =20 -static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_dh= ); } =20 -static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_s= s); } =20 -static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_d= s); } =20 -static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_s= d); } =20 -static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a) { return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_d= d); } @@ -4538,7 +4519,7 @@ static void do_str(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) tcg_temp_free_i64(t0); } =20 -static bool trans_LDR_zri(DisasContext *s, arg_rri *a, uint32_t insn) +static bool trans_LDR_zri(DisasContext *s, arg_rri *a) { if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); @@ -4548,7 +4529,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a= , uint32_t insn) return true; } =20 -static bool trans_LDR_pri(DisasContext *s, arg_rri *a, uint32_t insn) +static bool trans_LDR_pri(DisasContext *s, arg_rri *a) { if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); @@ -4558,7 +4539,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a= , uint32_t insn) return true; } =20 -static bool trans_STR_zri(DisasContext *s, arg_rri *a, uint32_t insn) +static bool trans_STR_zri(DisasContext *s, arg_rri *a) { if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); @@ -4568,7 +4549,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a= , uint32_t insn) return true; } =20 -static bool trans_STR_pri(DisasContext *s, arg_rri *a, uint32_t insn) +static bool trans_STR_pri(DisasContext *s, arg_rri *a) { if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); @@ -4693,7 +4674,7 @@ static void do_ld_zpa(DisasContext *s, int zt, int pg, do_mem_zpa(s, zt, pg, addr, dtype, fn); } =20 -static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn) +static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a) { if (a->rm =3D=3D 31) { return false; @@ -4707,7 +4688,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_l= oad *a, uint32_t insn) return true; } =20 -static bool trans_LD_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn) +static bool trans_LD_zpri(DisasContext *s, arg_rpri_load *a) { if (sve_access_check(s)) { int vsz =3D vec_full_reg_size(s); @@ -4722,7 +4703,7 @@ static bool trans_LD_zpri(DisasContext *s, arg_rpri_l= oad *a, uint32_t insn) return true; } =20 -static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a, uint32_t i= nsn) +static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a) { static gen_helper_gvec_mem * const fns[2][16] =3D { /* Little-endian */ @@ -4778,7 +4759,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rpr= r_load *a, uint32_t insn) return true; } =20 -static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a, uint32_t i= nsn) +static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a) { static gen_helper_gvec_mem * const fns[2][16] =3D { /* Little-endian */ @@ -4890,7 +4871,7 @@ static void do_ldrq(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int msz) } } =20 -static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a, uint32_t i= nsn) +static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a) { if (a->rm =3D=3D 31) { return false; @@ -4905,7 +4886,7 @@ static bool trans_LD1RQ_zprr(DisasContext *s, arg_rpr= r_load *a, uint32_t insn) return true; } =20 -static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a, uint32_t i= nsn) +static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a) { if (sve_access_check(s)) { TCGv_i64 addr =3D new_tmp_a64(s); @@ -4916,7 +4897,7 @@ static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpr= i_load *a, uint32_t insn) } =20 /* Load and broadcast element. */ -static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t in= sn) +static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) { if (!sve_access_check(s)) { return true; @@ -5036,7 +5017,7 @@ static void do_st_zpa(DisasContext *s, int zt, int pg= , TCGv_i64 addr, do_mem_zpa(s, zt, pg, addr, msz_dtype(msz), fn); } =20 -static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t ins= n) +static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) { if (a->rm =3D=3D 31 || a->msz > a->esz) { return false; @@ -5050,7 +5031,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_s= tore *a, uint32_t insn) return true; } =20 -static bool trans_ST_zpri(DisasContext *s, arg_rpri_store *a, uint32_t ins= n) +static bool trans_ST_zpri(DisasContext *s, arg_rpri_store *a) { if (a->msz > a->esz) { return false; @@ -5264,7 +5245,7 @@ static gen_helper_gvec_mem_scatter * const gather_loa= d_fn64[2][2][3][2][4] =3D { gen_helper_sve_ldffdd_be_zd, } } } }, }; =20 -static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a, uint32_t insn) +static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a) { gen_helper_gvec_mem_scatter *fn =3D NULL; int be =3D s->be_data =3D=3D MO_BE; @@ -5288,7 +5269,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_z= prz *a, uint32_t insn) return true; } =20 -static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a, uint32_t insn) +static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) { gen_helper_gvec_mem_scatter *fn =3D NULL; int be =3D s->be_data =3D=3D MO_BE; @@ -5368,7 +5349,7 @@ static gen_helper_gvec_mem_scatter * const scatter_st= ore_fn64[2][3][4] =3D { gen_helper_sve_stdd_be_zd, } }, }; =20 -static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn) +static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a) { gen_helper_gvec_mem_scatter *fn; int be =3D s->be_data =3D=3D MO_BE; @@ -5394,7 +5375,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_z= prz *a, uint32_t insn) return true; } =20 -static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn) +static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) { gen_helper_gvec_mem_scatter *fn =3D NULL; int be =3D s->be_data =3D=3D MO_BE; @@ -5430,14 +5411,14 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1= _zpiz *a, uint32_t insn) * Prefetches */ =20 -static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn) +static bool trans_PRF(DisasContext *s, arg_PRF *a) { /* Prefetch is a nop within QEMU. */ (void)sve_access_check(s); return true; } =20 -static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn) +static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a) { if (a->rm =3D=3D 31) { return false; @@ -5461,12 +5442,12 @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_r= r *a, uint32_t insn) * In the meantime, just emit the moves. */ =20 -static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a, uint32_t insn) +static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a) { return do_mov_z(s, a->rd, a->rn); } =20 -static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a) { if (sve_access_check(s)) { do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz); @@ -5474,7 +5455,7 @@ static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_= esz *a, uint32_t insn) return true; } =20 -static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a) { if (sve_access_check(s)) { do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz); diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c index 4bfd2dd8a6..bc63093ee9 100644 --- a/target/openrisc/disas.c +++ b/target/openrisc/disas.c @@ -51,12 +51,11 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *inf= o) return 4; } =20 -#define INSN(opcode, format, ...) \ -static bool trans_l_##opcode(disassemble_info *info, \ - arg_l_##opcode *a, uint32_t insn) \ -{ \ - output("l." #opcode, format, ##__VA_ARGS__); \ - return true; \ +#define INSN(opcode, format, ...) \ +static bool trans_l_##opcode(disassemble_info *info, arg_l_##opcode *a) \ +{ \ + output("l." #opcode, format, ##__VA_ARGS__); \ + return true; \ } =20 INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b) @@ -146,12 +145,12 @@ INSN(psync, "") INSN(csync, "") INSN(rfe, "") =20 -#define FP_INSN(opcode, suffix, format, ...) \ -static bool trans_lf_##opcode##_##suffix(disassemble_info *info, \ - arg_lf_##opcode##_##suffix *a, uint32_t insn) \ -{ \ - output("lf." #opcode "." #suffix, format, ##__VA_ARGS__); \ - return true; \ +#define FP_INSN(opcode, suffix, format, ...) \ +static bool trans_lf_##opcode##_##suffix(disassemble_info *info, \ + arg_lf_##opcode##_##suffix *a) \ +{ \ + output("lf." #opcode "." #suffix, format, ##__VA_ARGS__); \ + return true; \ } =20 FP_INSN(add, s, "r%d, r%d, r%d", a->d, a->a, a->b) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a271cd3903..c089914d6a 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -434,105 +434,105 @@ static void gen_msbu(DisasContext *dc, TCGv srca, T= CGv srcb) gen_ove_cy(dc); } =20 -static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_add(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_addc(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_sub(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_and(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_or(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_xor(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_sll(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_srl(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_sra(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_ror(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn) +static bool trans_l_exths(DisasContext *dc, arg_da *a) { check_r0_write(a->d); tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]); return true; } =20 -static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn) +static bool trans_l_extbs(DisasContext *dc, arg_da *a) { check_r0_write(a->d); tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]); return true; } =20 -static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn) +static bool trans_l_exthz(DisasContext *dc, arg_da *a) { check_r0_write(a->d); tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]); return true; } =20 -static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn) +static bool trans_l_extbz(DisasContext *dc, arg_da *a) { check_r0_write(a->d); tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]); return true; } =20 -static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_cmov(DisasContext *dc, arg_dab *a) { TCGv zero; =20 @@ -544,7 +544,7 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a, = uint32_t insn) return true; } =20 -static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn) +static bool trans_l_ff1(DisasContext *dc, arg_da *a) { check_r0_write(a->d); tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1); @@ -552,7 +552,7 @@ static bool trans_l_ff1(DisasContext *dc, arg_da *a, ui= nt32_t insn) return true; } =20 -static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn) +static bool trans_l_fl1(DisasContext *dc, arg_da *a) { check_r0_write(a->d); tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS); @@ -560,47 +560,47 @@ static bool trans_l_fl1(DisasContext *dc, arg_da *a, = uint32_t insn) return true; } =20 -static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_mul(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); gen_mul(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_mulu(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); gen_mulu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_div(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); gen_div(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_l_divu(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); gen_divu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_muld(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_l_muld(DisasContext *dc, arg_ab *a) { gen_muld(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_muldu(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_l_muldu(DisasContext *dc, arg_ab *a) { gen_muldu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn) +static bool trans_l_j(DisasContext *dc, arg_l_j *a) { target_ulong tmp_pc =3D dc->base.pc_next + a->n * 4; =20 @@ -610,7 +610,7 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uin= t32_t insn) return true; } =20 -static bool trans_l_jal(DisasContext *dc, arg_l_jal *a, uint32_t insn) +static bool trans_l_jal(DisasContext *dc, arg_l_jal *a) { target_ulong tmp_pc =3D dc->base.pc_next + a->n * 4; target_ulong ret_pc =3D dc->base.pc_next + 8; @@ -640,26 +640,26 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGC= ond cond) dc->delayed_branch =3D 2; } =20 -static bool trans_l_bf(DisasContext *dc, arg_l_bf *a, uint32_t insn) +static bool trans_l_bf(DisasContext *dc, arg_l_bf *a) { do_bf(dc, a, TCG_COND_NE); return true; } =20 -static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a, uint32_t insn) +static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a) { do_bf(dc, a, TCG_COND_EQ); return true; } =20 -static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn) +static bool trans_l_jr(DisasContext *dc, arg_l_jr *a) { tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); dc->delayed_branch =3D 2; return true; } =20 -static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a, uint32_t insn) +static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a) { tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8); @@ -667,7 +667,7 @@ static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *= a, uint32_t insn) return true; } =20 -static bool trans_l_lwa(DisasContext *dc, arg_load *a, uint32_t insn) +static bool trans_l_lwa(DisasContext *dc, arg_load *a) { TCGv ea; =20 @@ -692,43 +692,43 @@ static void do_load(DisasContext *dc, arg_load *a, TC= GMemOp mop) tcg_temp_free(ea); } =20 -static bool trans_l_lwz(DisasContext *dc, arg_load *a, uint32_t insn) +static bool trans_l_lwz(DisasContext *dc, arg_load *a) { do_load(dc, a, MO_TEUL); return true; } =20 -static bool trans_l_lws(DisasContext *dc, arg_load *a, uint32_t insn) +static bool trans_l_lws(DisasContext *dc, arg_load *a) { do_load(dc, a, MO_TESL); return true; } =20 -static bool trans_l_lbz(DisasContext *dc, arg_load *a, uint32_t insn) +static bool trans_l_lbz(DisasContext *dc, arg_load *a) { do_load(dc, a, MO_UB); return true; } =20 -static bool trans_l_lbs(DisasContext *dc, arg_load *a, uint32_t insn) +static bool trans_l_lbs(DisasContext *dc, arg_load *a) { do_load(dc, a, MO_SB); return true; } =20 -static bool trans_l_lhz(DisasContext *dc, arg_load *a, uint32_t insn) +static bool trans_l_lhz(DisasContext *dc, arg_load *a) { do_load(dc, a, MO_TEUW); return true; } =20 -static bool trans_l_lhs(DisasContext *dc, arg_load *a, uint32_t insn) +static bool trans_l_lhs(DisasContext *dc, arg_load *a) { do_load(dc, a, MO_TESW); return true; } =20 -static bool trans_l_swa(DisasContext *dc, arg_store *a, uint32_t insn) +static bool trans_l_swa(DisasContext *dc, arg_store *a) { TCGv ea, val; TCGLabel *lab_fail, *lab_done; @@ -771,30 +771,30 @@ static void do_store(DisasContext *dc, arg_store *a, = TCGMemOp mop) tcg_temp_free(t0); } =20 -static bool trans_l_sw(DisasContext *dc, arg_store *a, uint32_t insn) +static bool trans_l_sw(DisasContext *dc, arg_store *a) { do_store(dc, a, MO_TEUL); return true; } =20 -static bool trans_l_sb(DisasContext *dc, arg_store *a, uint32_t insn) +static bool trans_l_sb(DisasContext *dc, arg_store *a) { do_store(dc, a, MO_UB); return true; } =20 -static bool trans_l_sh(DisasContext *dc, arg_store *a, uint32_t insn) +static bool trans_l_sh(DisasContext *dc, arg_store *a) { do_store(dc, a, MO_TEUW); return true; } =20 -static bool trans_l_nop(DisasContext *dc, arg_l_nop *a, uint32_t insn) +static bool trans_l_nop(DisasContext *dc, arg_l_nop *a) { return true; } =20 -static bool trans_l_addi(DisasContext *dc, arg_rri *a, uint32_t insn) +static bool trans_l_addi(DisasContext *dc, arg_rri *a) { TCGv t0; =20 @@ -805,7 +805,7 @@ static bool trans_l_addi(DisasContext *dc, arg_rri *a, = uint32_t insn) return true; } =20 -static bool trans_l_addic(DisasContext *dc, arg_rri *a, uint32_t insn) +static bool trans_l_addic(DisasContext *dc, arg_rri *a) { TCGv t0; =20 @@ -816,7 +816,7 @@ static bool trans_l_addic(DisasContext *dc, arg_rri *a,= uint32_t insn) return true; } =20 -static bool trans_l_muli(DisasContext *dc, arg_rri *a, uint32_t insn) +static bool trans_l_muli(DisasContext *dc, arg_rri *a) { TCGv t0; =20 @@ -827,7 +827,7 @@ static bool trans_l_muli(DisasContext *dc, arg_rri *a, = uint32_t insn) return true; } =20 -static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn) +static bool trans_l_maci(DisasContext *dc, arg_l_maci *a) { TCGv t0; =20 @@ -837,28 +837,28 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci= *a, uint32_t insn) return true; } =20 -static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn) +static bool trans_l_andi(DisasContext *dc, arg_rrk *a) { check_r0_write(a->d); tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k); return true; } =20 -static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn) +static bool trans_l_ori(DisasContext *dc, arg_rrk *a) { check_r0_write(a->d); tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k); return true; } =20 -static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn) +static bool trans_l_xori(DisasContext *dc, arg_rri *a) { check_r0_write(a->d); tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) +static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) { check_r0_write(a->d); =20 @@ -873,7 +873,7 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr= *a, uint32_t insn) return true; } =20 -static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) +static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) { if (is_user(dc)) { gen_illegal_exception(dc); @@ -901,66 +901,66 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mts= pr *a, uint32_t insn) return true; } =20 -static bool trans_l_mac(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_l_mac(DisasContext *dc, arg_ab *a) { gen_mac(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_msb(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_l_msb(DisasContext *dc, arg_ab *a) { gen_msb(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_macu(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_l_macu(DisasContext *dc, arg_ab *a) { gen_macu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_l_msbu(DisasContext *dc, arg_ab *a) { gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn) +static bool trans_l_slli(DisasContext *dc, arg_dal *a) { check_r0_write(a->d); tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); return true; } =20 -static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn) +static bool trans_l_srli(DisasContext *dc, arg_dal *a) { check_r0_write(a->d); tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); return true; } =20 -static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn) +static bool trans_l_srai(DisasContext *dc, arg_dal *a) { check_r0_write(a->d); tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1= )); return true; } =20 -static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn) +static bool trans_l_rori(DisasContext *dc, arg_dal *a) { check_r0_write(a->d); tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - = 1)); return true; } =20 -static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn) +static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a) { check_r0_write(a->d); tcg_gen_movi_tl(cpu_R[a->d], a->k << 16); return true; } =20 -static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn) +static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a) { check_r0_write(a->d); tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac); @@ -968,127 +968,127 @@ static bool trans_l_macrc(DisasContext *dc, arg_l_m= acrc *a, uint32_t insn) return true; } =20 -static bool trans_l_sfeq(DisasContext *dc, arg_ab *a, TCGCond cond) +static bool trans_l_sfeq(DisasContext *dc, arg_ab *a) { tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sfne(DisasContext *dc, arg_ab *a, TCGCond cond) +static bool trans_l_sfne(DisasContext *dc, arg_ab *a) { tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a, TCGCond cond) +static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a) { tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a, TCGCond cond) +static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a) { tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sfltu(DisasContext *dc, arg_ab *a, TCGCond cond) +static bool trans_l_sfltu(DisasContext *dc, arg_ab *a) { tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sfleu(DisasContext *dc, arg_ab *a, TCGCond cond) +static bool trans_l_sfleu(DisasContext *dc, arg_ab *a) { tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sfgts(DisasContext *dc, arg_ab *a, TCGCond cond) +static bool trans_l_sfgts(DisasContext *dc, arg_ab *a) { tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sfges(DisasContext *dc, arg_ab *a, TCGCond cond) +static bool trans_l_sfges(DisasContext *dc, arg_ab *a) { tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sflts(DisasContext *dc, arg_ab *a, TCGCond cond) +static bool trans_l_sflts(DisasContext *dc, arg_ab *a) { tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond) +static bool trans_l_sfles(DisasContext *dc, arg_ab *a) { tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } =20 -static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a, TCGCond cond) +static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a) { tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_sfnei(DisasContext *dc, arg_ai *a, TCGCond cond) +static bool trans_l_sfnei(DisasContext *dc, arg_ai *a) { tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a, TCGCond cond) +static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a) { tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a, TCGCond cond) +static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a) { tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_sfltui(DisasContext *dc, arg_ai *a, TCGCond cond) +static bool trans_l_sfltui(DisasContext *dc, arg_ai *a) { tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_sfleui(DisasContext *dc, arg_ai *a, TCGCond cond) +static bool trans_l_sfleui(DisasContext *dc, arg_ai *a) { tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a, TCGCond cond) +static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a) { tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a, TCGCond cond) +static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a) { tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a, TCGCond cond) +static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a) { tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_sflesi(DisasContext *dc, arg_ai *a, TCGCond cond) +static bool trans_l_sflesi(DisasContext *dc, arg_ai *a) { tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i); return true; } =20 -static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) +static bool trans_l_sys(DisasContext *dc, arg_l_sys *a) { tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_SYSCALL); @@ -1096,7 +1096,7 @@ static bool trans_l_sys(DisasContext *dc, arg_l_sys *= a, uint32_t insn) return true; } =20 -static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn) +static bool trans_l_trap(DisasContext *dc, arg_l_trap *a) { tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_TRAP); @@ -1104,23 +1104,23 @@ static bool trans_l_trap(DisasContext *dc, arg_l_tr= ap *a, uint32_t insn) return true; } =20 -static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn) +static bool trans_l_msync(DisasContext *dc, arg_l_msync *a) { tcg_gen_mb(TCG_MO_ALL); return true; } =20 -static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn) +static bool trans_l_psync(DisasContext *dc, arg_l_psync *a) { return true; } =20 -static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn) +static bool trans_l_csync(DisasContext *dc, arg_l_csync *a) { return true; } =20 -static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) +static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a) { if (is_user(dc)) { gen_illegal_exception(dc); @@ -1162,49 +1162,49 @@ static void do_fpcmp(DisasContext *dc, arg_ab *a, gen_helper_update_fpcsr(cpu_env); } =20 -static bool trans_lf_add_s(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_lf_add_s(DisasContext *dc, arg_dab *a) { do_fp3(dc, a, gen_helper_float_add_s); return true; } =20 -static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a) { do_fp3(dc, a, gen_helper_float_sub_s); return true; } =20 -static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a) { do_fp3(dc, a, gen_helper_float_mul_s); return true; } =20 -static bool trans_lf_div_s(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_lf_div_s(DisasContext *dc, arg_dab *a) { do_fp3(dc, a, gen_helper_float_div_s); return true; } =20 -static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a) { do_fp3(dc, a, gen_helper_float_rem_s); return true; } =20 -static bool trans_lf_itof_s(DisasContext *dc, arg_da *a, uint32_t insn) +static bool trans_lf_itof_s(DisasContext *dc, arg_da *a) { do_fp2(dc, a, gen_helper_itofs); return true; } =20 -static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a, uint32_t insn) +static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a) { do_fp2(dc, a, gen_helper_ftois); return true; } =20 -static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn) +static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a) { check_r0_write(a->d); gen_helper_float_madd_s(cpu_R[a->d], cpu_env, cpu_R[a->d], @@ -1213,37 +1213,37 @@ static bool trans_lf_madd_s(DisasContext *dc, arg_d= ab *a, uint32_t insn) return true; } =20 -static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a) { do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); return true; } =20 -static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a) { do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); return true; } =20 -static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a) { do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); return true; } =20 -static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a) { do_fpcmp(dc, a, gen_helper_float_le_s, false, true); return true; } =20 -static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a) { do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); return true; } =20 -static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn) +static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a) { do_fpcmp(dc, a, gen_helper_float_le_s, false, false); return true; diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 28bbd4e3c1..6670d58cc1 100755 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -466,8 +466,7 @@ class Pattern(General): output('typedef ', self.base.base.struct_name(), ' arg_', self.name, ';\n') output(translate_scope, 'bool ', translate_prefix, '_', self.name, - '(DisasContext *ctx, arg_', self.name, - ' *a, ', insntype, ' insn);\n') + '(DisasContext *ctx, arg_', self.name, ' *a);\n') =20 def output_code(self, i, extracted, outerbits, outermask): global translate_prefix @@ -479,7 +478,7 @@ class Pattern(General): for n, f in self.fields.items(): output(ind, 'u.f_', arg, '.', n, ' =3D ', f.str_extract(), ';\= n') output(ind, 'return ', translate_prefix, '_', self.name, - '(ctx, &u.f_', arg, ', insn);\n') + '(ctx, &u.f_', arg, ');\n') # end Pattern =20 =20 --=20 2.17.2 From nobody Fri May 3 01:29:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[79.69.241.110]) by smtp.gmail.com with ESMTPSA id u5-v6sm7580168wrm.77.2018.10.31.09.53.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Oct 2018 09:53:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JIUdfi8Wiee3VEFA1DC9zFaD8+pHIsuCf9eAvQVoCks=; b=g6rNW59TEzwIINCPPEP1E1RMyzltgWa3sUAzosuH+nJtWtn+kMQ3GVYCA4LPsIX+HF pvsTIqzEtbqDsssXnzND6T+Yrbp0GGtUCcVo28fXulcQtAtPBbcwRe1RiTrXwtBk3eya qkln/rlwCh5YEUTk70mknRmE+c7Sr9iz8TGVA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JIUdfi8Wiee3VEFA1DC9zFaD8+pHIsuCf9eAvQVoCks=; b=Bfmasa+DkHm8yOS0MF7MXuSEAO3/kkm9Rkppe78vTJoiTtFkcsqG1wUwYdtegnphxf kSLMEtRX7ngsKl42z7RN8FS+N+9819qbLT7oI/l6l8RysJ1gnkC1SxlCAP/EvPpm5rlS Di3TMrfC/uK0uXgjp3IqW+Bv75gEgvDPOqPsc0N7GD5cDBfQgNRvyWe3kVLG2HstBkuy +sYcUCDgJBXQhRz8AfPxPgr56cES9hX1linVhms7UhsvVr4JDNDk2LZ88W7Z1E2sx093 ena6lHKZvbTMb/UkcqxmGI0t2KS76l1Qv917PueaUG1IkjIqy5fDB6TlWUemecWv9ZTL qLLw== X-Gm-Message-State: AGRZ1gJjyxJkpmwYQvIvrbxSKiYslDwMuWL3IMa7ZEdojgsQQXQ2fgyD SVdA0T7erBxKWgSRRqMBrmAP1qEIwQw= X-Google-Smtp-Source: AJdET5f4fK5yigJ+fjgfPosN7f6yd1VvWV8pjOrBKjLrMtJxpG4phqbepnMROhtIfnCvYb8K1gSioQ== X-Received: by 2002:a1c:2846:: with SMTP id o67-v6mr2936882wmo.60.1541004807177; Wed, 31 Oct 2018 09:53:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 31 Oct 2018 16:53:21 +0000 Message-Id: <20181031165321.4422-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181031165321.4422-1-richard.henderson@linaro.org> References: <20181031165321.4422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 3/3] decodetree: Allow multiple input files X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) While it would be possible to concatenate input files with make, passing the original input files to decodetree.py allows us to generate error messages which allows compilation environments (read: emacs) to next-error to the correct input file. Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- scripts/decodetree.py | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 6670d58cc1..4a3d46e4a7 100755 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -175,15 +175,15 @@ decode_function =3D 'decode' re_ident =3D '[a-zA-Z][a-zA-Z0-9_]*' =20 =20 -def error(lineno, *args): +def error_with_file(file, lineno, *args): """Print an error message from file:line and args and exit.""" global output_file global output_fd =20 if lineno: - r =3D '{0}:{1}: error:'.format(input_file, lineno) + r =3D '{0}:{1}: error:'.format(file, lineno) elif input_file: - r =3D '{0}: error:'.format(input_file) + r =3D '{0}: error:'.format(file) else: r =3D 'error:' for a in args: @@ -195,6 +195,8 @@ def error(lineno, *args): os.remove(output_file) exit(1) =20 +def error(lineno, *args): + error_with_file(input_file, lineno, args) =20 def output(*args): global output_fd @@ -420,6 +422,7 @@ class General: """Common code between instruction formats and instruction patterns""" def __init__(self, name, lineno, base, fixb, fixm, udfm, fldm, flds): self.name =3D name + self.file =3D input_file self.lineno =3D lineno self.base =3D base self.fixedbits =3D fixb @@ -472,7 +475,7 @@ class Pattern(General): global translate_prefix ind =3D str_indent(i) arg =3D self.base.base.name - output(ind, '/* line ', str(self.lineno), ' */\n') + output(ind, '/* ', self.file, ':', str(self.lineno), ' */\n') if not extracted: output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);= \n') for n, f in self.fields.items(): @@ -920,8 +923,9 @@ def build_tree(pats, outerbits, outermask): if innermask =3D=3D 0: pnames =3D [] for p in pats: - pnames.append(p.name + ':' + str(p.lineno)) - error(pats[0].lineno, 'overlapping patterns:', pnames) + pnames.append(p.name + ':' + p.file + ':' + str(p.lineno)) + error_with_file(pats[0].file, pats[0].lineno, + 'overlapping patterns:', pnames) =20 fullmask =3D outermask | innermask =20 @@ -1012,10 +1016,11 @@ def main(): =20 if len(args) < 1: error(0, 'missing input file') - input_file =3D args[0] - f =3D open(input_file, 'r') - parse_file(f) - f.close() + for filename in args: + input_file =3D filename + f =3D open(filename, 'r') + parse_file(f) + f.close() =20 t =3D build_tree(patterns, 0, 0) prop_format(t) --=20 2.17.2