[Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree

Bastian Koppelmann posted 35 patches 5 years, 4 months ago
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target/riscv/Makefile.objs                    |   22 +
target/riscv/insn16-32.decode                 |   31 +
target/riscv/insn16-64.decode                 |   33 +
target/riscv/insn16.decode                    |  114 ++
target/riscv/insn32.decode                    |  203 ++
target/riscv/insn64.decode                    |   72 +
.../riscv/insn_trans/trans_privileged.inc.c   |  108 +
target/riscv/insn_trans/trans_rva.inc.c       |  203 ++
target/riscv/insn_trans/trans_rvc.inc.c       |  149 ++
target/riscv/insn_trans/trans_rvd.inc.c       |  388 ++++
target/riscv/insn_trans/trans_rvf.inc.c       |  388 ++++
target/riscv/insn_trans/trans_rvi.inc.c       |  584 ++++++
target/riscv/insn_trans/trans_rvm.inc.c       |  107 +
target/riscv/translate.c                      | 1771 ++---------------
14 files changed, 2615 insertions(+), 1558 deletions(-)
create mode 100644 target/riscv/insn16-32.decode
create mode 100644 target/riscv/insn16-64.decode
create mode 100644 target/riscv/insn16.decode
create mode 100644 target/riscv/insn32.decode
create mode 100644 target/riscv/insn64.decode
create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
[Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree
Posted by Bastian Koppelmann 5 years, 4 months ago
Hi,

this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-16]:
    Many of the gen_* functions are called by the decode functions for 16-bit
    and 32-bit functions. If we move translation code from the gen_*
    functions to the generated trans_* functions of decode-tree, we get a lot of
    duplication. Therefore, we mostly generate calls to the old gen_* function
    which are properly replaced after step 2).

    Each of the trans_ functions are grouped into files corresponding to their
    ISA extension, e.g. addi which is in RV32I is translated in the file
    'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 17-19]:
    All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
    we convert the arguments in the 16 bit trans_ function to the arguments of
    the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 20-30]:
    this move all manual translation code into the trans_* instructions of
    decode tree, such that we can remove the old decode_* functions.

4) Simply RVC by reusing as much as possible from the RVG decoder as suggested
   by Richard. [Patch 31-35]

this series depends on the decodetree patches by Richard:
https://github.com/rth7680/qemu/tree/decodetree

full tree available at
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v3

Cheers,
Bastian

v2 -> v3:
   - ex_shift_amount returns int
   - dropped insn argument of trans_foo functions
   - removal of AUIPC moved to 0002
   - &branch -> &b
   - split 0004 into two patches for RV32 and RV64
   - moved 64-bit only insn to insn64.decode
   - removed %pred/%succ
   - dropped TARGET_RISCV64 requirement for fclass_d
   - illegal instruction call replaced with return false
   - trans_c_flw_ld and trans_c_fsw_sd now return false for now, as we
     cannot use the insn argument anymore for manual decoding. We fix this
     in a later patch when rvc is properly split up into insn16-32.decode
     and insn16-64.decode.
   - special case of trans_c_addi4spn() returns false in this patch
   - simplified trans_c_srai by Richard's suggestion
   - Since trans_c_flw_ld and trans_c_fsw_sd still rely on the old decoder
     we need to keep gen_load(). Thus we renamed it to gen_load_c.
   - Since trans_c_flw_ld and trans_c_fsw_sd still rely on the old decoder
     we need to keep gen_store(). Thus we renamed it to gen_store_c.
   - tcg_memop_lookup is now only used by TARGET_RISCV64 insn so we wrapped
     it in a ifdef
   - trans_srli/srai now use tcg_gen_shri/srai_tl
   - trans_addiw uses its own gen_addiw function which properly extends the
     result
   - &arith_imm -> &i
   - &arith -> &r
   - trans_mulw now uses gen_mulw which properly sign extends the result
   - gen_arith_w -> gen_arith_div_w
   - gen_arith_div_w properly sign extends the resul


Bastian Koppelmann (35):
  target/riscv: Move CPURISCVState pointer to DisasContext
  target/riscv: Activate decodetree and implemnt LUI & AUIPC
  target/riscv: Convert RVXI branch insns to decodetree
  target/riscv: Convert RV32I load/store insns to decodetree
  target/riscv: Convert RV64I load/store insns to decodetree
  target/riscv: Convert RVXI arithmetic insns to decodetree
  target/riscv: Convert RVXI fence insns to decodetree
  target/riscv: Convert RVXI csr insns to decodetree
  target/riscv: Convert RVXM insns to decodetree
  target/riscv: Convert RV32A insns to decodetree
  target/riscv: Convert RV64A insns to decodetree
  target/riscv: Convert RV32F insns to decodetree
  target/riscv: Convert RV64F insns to decodetree
  target/riscv: Convert RV32D insns to decodetree
  target/riscv: Convert RV64D insns to decodetree
  target/riscv: Convert RV priv insns to decodetree
  target/riscv: Convert quadrant 0 of RVXC insns to decodetree
  target/riscv: Convert quadrant 1 of RVXC insns to decodetree
  target/riscv: Convert quadrant 2 of RVXC insns to decodetree
  target/riscv: Remove gen_jalr()
  target/riscv: Remove manual decoding from gen_branch()
  target/riscv: Remove manual decoding from gen_load()
  target/riscv: Remove manual decoding from gen_store()
  target/riscv: Move gen_arith_imm() decoding into trans_* functions
  target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
  target/riscv: Remove shift and slt insn manual decoding
  target/riscv: Remove manual decoding of RV32/64M insn
  target/riscv: Rename trans_arith to gen_arith
  target/riscv: Remove gen_system()
  target/riscv: Remove decode_RV32_64G()
  target/riscv: Convert @cs_2 insns to share translation functions
  target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
  target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
  target/riscv: Splice remaining compressed insn pairs for riscv32 vs
    riscv64
  target/riscv: Remaining rvc insn reuse 32 bit translators

 target/riscv/Makefile.objs                    |   22 +
 target/riscv/insn16-32.decode                 |   31 +
 target/riscv/insn16-64.decode                 |   33 +
 target/riscv/insn16.decode                    |  114 ++
 target/riscv/insn32.decode                    |  203 ++
 target/riscv/insn64.decode                    |   72 +
 .../riscv/insn_trans/trans_privileged.inc.c   |  108 +
 target/riscv/insn_trans/trans_rva.inc.c       |  203 ++
 target/riscv/insn_trans/trans_rvc.inc.c       |  149 ++
 target/riscv/insn_trans/trans_rvd.inc.c       |  388 ++++
 target/riscv/insn_trans/trans_rvf.inc.c       |  388 ++++
 target/riscv/insn_trans/trans_rvi.inc.c       |  584 ++++++
 target/riscv/insn_trans/trans_rvm.inc.c       |  107 +
 target/riscv/translate.c                      | 1771 ++---------------
 14 files changed, 2615 insertions(+), 1558 deletions(-)
 create mode 100644 target/riscv/insn16-32.decode
 create mode 100644 target/riscv/insn16-64.decode
 create mode 100644 target/riscv/insn16.decode
 create mode 100644 target/riscv/insn32.decode
 create mode 100644 target/riscv/insn64.decode
 create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c

-- 
2.19.1


Re: [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree
Posted by no-reply@patchew.org 5 years, 4 months ago
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20181031132029.4887-1-kbastian@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v3 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
0dc9aaa65c target/riscv: Remaining rvc insn reuse 32 bit translators
8d508e3f89 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
44e80c8498 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
07f644d3a2 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
40b6158d54 target/riscv: Convert @cs_2 insns to share translation functions
ca95ca92a5 target/riscv: Remove decode_RV32_64G()
666c42149b target/riscv: Remove gen_system()
e1892386ec target/riscv: Rename trans_arith to gen_arith
1b33908223 target/riscv: Remove manual decoding of RV32/64M insn
1a5fef8c4e target/riscv: Remove shift and slt insn manual decoding
2731f425de target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
9c34cbd280 target/riscv: Move gen_arith_imm() decoding into trans_* functions
2eaf68ef78 target/riscv: Remove manual decoding from gen_store()
31f0d4c241 target/riscv: Remove manual decoding from gen_load()
9d725fe480 target/riscv: Remove manual decoding from gen_branch()
9d8e1f844c target/riscv: Remove gen_jalr()
dc3753ad33 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
1a083b100e target/riscv: Convert quadrant 1 of RVXC insns to decodetree
b831b8c4ec target/riscv: Convert quadrant 0 of RVXC insns to decodetree
c931914bd2 target/riscv: Convert RV priv insns to decodetree
767d172f2d target/riscv: Convert RV64D insns to decodetree
18d3406ee6 target/riscv: Convert RV32D insns to decodetree
515c07059a target/riscv: Convert RV64F insns to decodetree
3506dbc10d target/riscv: Convert RV32F insns to decodetree
2197c6b6b1 target/riscv: Convert RV64A insns to decodetree
c07ae6248a target/riscv: Convert RV32A insns to decodetree
508bf988f6 target/riscv: Convert RVXM insns to decodetree
2773626354 target/riscv: Convert RVXI csr insns to decodetree
55033facbb target/riscv: Convert RVXI fence insns to decodetree
e4d5253c9f target/riscv: Convert RVXI arithmetic insns to decodetree
7616bcfe80 target/riscv: Convert RV64I load/store insns to decodetree
7a348ac675 target/riscv: Convert RV32I load/store insns to decodetree
68f5d736d1 target/riscv: Convert RVXI branch insns to decodetree
2b6fed94f8 target/riscv: Activate decodetree and implemnt LUI & AUIPC
5fa58ba15a target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
Checking PATCH 1/35: target/riscv: Move CPURISCVState pointer to DisasContext...
Checking PATCH 2/35: target/riscv: Activate decodetree and implemnt LUI & AUIPC...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#32: 
new file mode 100644

ERROR: externs should be avoided in .c files
#123: FILE: target/riscv/translate.c:1677:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 3/35: target/riscv: Convert RVXI branch insns to decodetree...
Checking PATCH 4/35: target/riscv: Convert RV32I load/store insns to decodetree...
Checking PATCH 5/35: target/riscv: Convert RV64I load/store insns to decodetree...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#37: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/35: target/riscv: Convert RVXI arithmetic insns to decodetree...
Checking PATCH 7/35: target/riscv: Convert RVXI fence insns to decodetree...
Checking PATCH 8/35: target/riscv: Convert RVXI csr insns to decodetree...
Checking PATCH 9/35: target/riscv: Convert RVXM insns to decodetree...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#46: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 10/35: target/riscv: Convert RV32A insns to decodetree...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51: 
new file mode 100644

total: 0 errors, 1 warnings, 184 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 11/35: target/riscv: Convert RV64A insns to decodetree...
Checking PATCH 12/35: target/riscv: Convert RV32F insns to decodetree...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#75: 
new file mode 100644

total: 0 errors, 1 warnings, 397 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 13/35: target/riscv: Convert RV64F insns to decodetree...
Checking PATCH 14/35: target/riscv: Convert RV32D insns to decodetree...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 353 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 15/35: target/riscv: Convert RV64D insns to decodetree...
Checking PATCH 16/35: target/riscv: Convert RV priv insns to decodetree...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#38: 
new file mode 100644

total: 0 errors, 1 warnings, 204 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 17/35: target/riscv: Convert quadrant 0 of RVXC insns to decodetree...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#29: 
new file mode 100644

ERROR: externs should be avoided in .c files
#244: FILE: target/riscv/translate.c:984:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 18/35: target/riscv: Convert quadrant 1 of RVXC insns to decodetree...
Checking PATCH 19/35: target/riscv: Convert quadrant 2 of RVXC insns to decodetree...
Checking PATCH 20/35: target/riscv: Remove gen_jalr()...
Checking PATCH 21/35: target/riscv: Remove manual decoding from gen_branch()...
Checking PATCH 22/35: target/riscv: Remove manual decoding from gen_load()...
Checking PATCH 23/35: target/riscv: Remove manual decoding from gen_store()...
Checking PATCH 24/35: target/riscv: Move gen_arith_imm() decoding into trans_* functions...
Checking PATCH 25/35: target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists...
Checking PATCH 26/35: target/riscv: Remove shift and slt insn manual decoding...
Checking PATCH 27/35: target/riscv: Remove manual decoding of RV32/64M insn...
Checking PATCH 28/35: target/riscv: Rename trans_arith to gen_arith...
Checking PATCH 29/35: target/riscv: Remove gen_system()...
Checking PATCH 30/35: target/riscv: Remove decode_RV32_64G()...
Checking PATCH 31/35: target/riscv: Convert @cs_2 insns to share translation functions...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#40: 
new file mode 100644

ERROR: externs should be avoided in .c files
#180: FILE: target/riscv/translate.c:494:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 32/35: target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns...
Checking PATCH 33/35: target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#25: 
new file mode 100644

total: 0 errors, 1 warnings, 287 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 34/35: target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64...
Checking PATCH 35/35: target/riscv: Remaining rvc insn reuse 32 bit translators...
=== OUTPUT END ===

Test command exited with code: 1


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