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[79.69.241.110]) by smtp.gmail.com with ESMTPSA id v2-v6sm13450362wru.17.2018.10.31.05.21.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Oct 2018 05:21:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qCyLB+n5EKVJXBopQEFZ+OzjPMF9tnCVECySDJjBV9c=; b=EvBAOR8Pgw0WuSyve9PVJZXGXMnEH640FnJ46PM0OrAQv8yNyktRwNOLKRzsM/En2A yBFXm0XAseWULPfGbophDxRxnF41Cm4ufVC45ehvcNnfPGHZq7PCFchc+1SzJ341X45w QVB7nD5a2sOasBdOFgujuwU2QgiRobS+EEyNM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qCyLB+n5EKVJXBopQEFZ+OzjPMF9tnCVECySDJjBV9c=; b=aQORqMx1FxG6eOkdpDhlmtQ0zot27fKn4aXO+Kky2ny05mIkRHECqn2x3Mmd0ckpQU pC2PHys9pnnv3bsXf5pWsfUs0RqRXzv6Nz/1iln8+6FTO3GI1J5pdt08/eY8YzL1i0y9 gKlc9yO7axYgyW2caESx3gCl09do87KzjMfACROLRol08GPt1zJqYKVo6U0+2PC2Fnpr FhqG/9TmR5XTVL+TO728+lhkE81PcmzaDFJ7HNcd/x9N6oyvAo5eGJvDp9IkzziZT3Rm Zo8fNJWKGRDuKYTuX0Sn+x9QqwS4OPN1sX+mm8Zsst+rvNitI8IjBZ6gL9vY5ZrL0b5U H5JQ== X-Gm-Message-State: AGRZ1gIo4pYtAvMwWtwsVznYtKGsgiZh2hAG6yCg2cLmmUrbfUL+V6DA wZfqWSgkoCqv/8VfMQcOYeSG9sjJduI= X-Google-Smtp-Source: AJdET5fMovOjw/sqHpDmZf/bkWL15gcP0uBHRrP5QMFqtUr6+761UXEpSUyain/Z6bCmRGfCb2JI3A== X-Received: by 2002:adf:d101:: with SMTP id a1-v6mr2745320wri.17.1540988481635; Wed, 31 Oct 2018 05:21:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 31 Oct 2018 12:21:10 +0000 Message-Id: <20181031122119.1669-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181031122119.1669-1-richard.henderson@linaro.org> References: <20181031122119.1669-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PULL 01/10] cputlb: Move tlb_lock to CPUTLBCommon X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is the first of several moves to reduce the size of the CPU_COMMON_TLB macro and improve some locality of refernce. Tested-by: Emilio G. Cota Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 17 ++++++++++++--- accel/tcg/cputlb.c | 48 ++++++++++++++++++++--------------------- 2 files changed, 38 insertions(+), 27 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 4ff62f32bf..9005923b4d 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -141,10 +141,21 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; =20 +/* + * Data elements that are shared between all MMU modes. + */ +typedef struct CPUTLBCommon { + /* lock serializes updates to tlb_table and tlb_v_table */ + QemuSpin lock; +} CPUTLBCommon; + +/* + * The meaning of each of the MMU modes is defined in the target code. + * Note that NB_MMU_MODES is not yet defined; we can only reference it + * within preprocessor defines that will be expanded later. + */ #define CPU_COMMON_TLB \ - /* The meaning of the MMU modes is defined in the target code. */ \ - /* tlb_lock serializes updates to tlb_table and tlb_v_table */ \ - QemuSpin tlb_lock; \ + CPUTLBCommon tlb_c; \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index af57aca5e4..d4e07056be 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -78,7 +78,7 @@ void tlb_init(CPUState *cpu) { CPUArchState *env =3D cpu->env_ptr; =20 - qemu_spin_init(&env->tlb_lock); + qemu_spin_init(&env->tlb_c.lock); } =20 /* flush_all_helper: run fn across all cpus @@ -134,15 +134,15 @@ static void tlb_flush_nocheck(CPUState *cpu) tlb_debug("(count: %zu)\n", tlb_flush_count()); =20 /* - * tlb_table/tlb_v_table updates from any thread must hold tlb_lock. + * tlb_table/tlb_v_table updates from any thread must hold tlb_c.lock. * However, updates from the owner thread (as is the case here; see the * above assert_cpu_is_self) do not need atomic_set because all reads * that do not hold the lock are performed by the same owner thread. */ - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 @@ -195,7 +195,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) =20 tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask); =20 - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { =20 if (test_bit(mmu_idx, &mmu_idx_bitmask)) { @@ -205,7 +205,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[= 0])); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 @@ -262,7 +262,7 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tl= b_entry, tlb_hit_page(tlb_entry->addr_code, page); } =20 -/* Called with tlb_lock held */ +/* Called with tlb_c.lock held */ static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, target_ulong page) { @@ -271,7 +271,7 @@ static inline void tlb_flush_entry_locked(CPUTLBEntry *= tlb_entry, } } =20 -/* Called with tlb_lock held */ +/* Called with tlb_c.lock held */ static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_i= dx, target_ulong page) { @@ -304,12 +304,12 @@ static void tlb_flush_page_async_work(CPUState *cpu, = run_on_cpu_data data) } =20 addr &=3D TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); =20 tb_flush_jmp_cache(cpu, addr); } @@ -345,14 +345,14 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSt= ate *cpu, tlb_debug("flush page addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n", addr, mmu_idx_bitmap); =20 - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); =20 tb_flush_jmp_cache(cpu, addr); } @@ -479,7 +479,7 @@ void tlb_unprotect_code(ram_addr_t ram_addr) * te->addr_write with atomic_set. We don't need to worry about this for * oversized guests as MTTCG is disabled for them. * - * Called with tlb_lock held. + * Called with tlb_c.lock held. */ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, uintptr_t start, uintptr_t length) @@ -501,7 +501,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *t= lb_entry, } =20 /* - * Called with tlb_lock held. + * Called with tlb_c.lock held. * Called only from the vCPU context, i.e. the TLB's owner thread. */ static inline void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntr= y *s) @@ -511,7 +511,7 @@ static inline void copy_tlb_helper_locked(CPUTLBEntry *= d, const CPUTLBEntry *s) =20 /* This is a cross vCPU call (i.e. another vCPU resetting the flags of * the target vCPU). - * We must take tlb_lock to avoid racing with another vCPU update. The only + * We must take tlb_c.lock to avoid racing with another vCPU update. The o= nly * thing actually updated is the target TLB entry ->addr_write flags. */ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) @@ -521,7 +521,7 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, = ram_addr_t length) int mmu_idx; =20 env =3D cpu->env_ptr; - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; =20 @@ -535,10 +535,10 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1= , ram_addr_t length) length); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); } =20 -/* Called with tlb_lock held */ +/* Called with tlb_c.lock held */ static inline void tlb_set_dirty1_locked(CPUTLBEntry *tlb_entry, target_ulong vaddr) { @@ -557,7 +557,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) assert_cpu_is_self(cpu); =20 vaddr &=3D TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr); } @@ -568,7 +568,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); } =20 /* Our TLB does not support large pages, so remember the area covered by @@ -669,7 +669,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, * a longer critical section, but this is not a concern since the TLB = lock * is unlikely to be contended. */ - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); =20 /* Make sure there's no cached translation for the new page. */ tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); @@ -736,7 +736,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, } =20 copy_tlb_helper_locked(te, &tn); - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); } =20 /* Add a new TLB entry, but without specifying the memory @@ -917,11 +917,11 @@ static bool victim_tlb_hit(CPUArchState *env, size_t = mmu_idx, size_t index, /* Found entry in victim tlb, swap tlb and iotlb. */ CPUTLBEntry tmptlb, *tlb =3D &env->tlb_table[mmu_idx][index]; =20 - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); copy_tlb_helper_locked(&tmptlb, tlb); copy_tlb_helper_locked(tlb, vtlb); copy_tlb_helper_locked(vtlb, &tmptlb); - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); =20 CPUIOTLBEntry tmpio, *io =3D &env->iotlb[mmu_idx][index]; CPUIOTLBEntry *vio =3D &env->iotlb_v[mmu_idx][vidx]; --=20 2.17.2