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[79.69.241.110]) by smtp.gmail.com with ESMTPSA id v2-v6sm13450362wru.17.2018.10.31.05.21.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Oct 2018 05:21:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q/yjo8z+g7lwII7MAY80uwlsqNxP5aVjMUM/ksqnyvc=; b=XbtsLZBbUDXxTOZGWz73kzMKoAJWHQS6KGA01KvPELR0F+kDJNmogqkZLQdwvinWwC Kb5181SqUxBliOMyzjH5Ti/zyHQRgRcvjtLn9HWKBx01ibsoKhFsBVrMMX5XyZ0SxsiK JcpWF7gjgcKWe8AqWHZKOZZwTVHiJWN5x9JLE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q/yjo8z+g7lwII7MAY80uwlsqNxP5aVjMUM/ksqnyvc=; b=t5+30K0SbpLsYGvCtD+7MkPoK0bNthB80tX/ew3cTx+xpMsAZsDvoMnvzEPrteBLMt krchYZ0LnPyVnHqfACc3oFgkZyPJ0dPXA80n/PhAyfe6xBdsf43rXP0k9MJijeU+rN+M 5oH/LxeFqVdXhGLmhJE4e2pJYckSWZlW78bV4yqv8Sj1eHF42wq2kLoJ6VjoJOtVMmV0 NYYMLGXiOshdWJJaI2QMjZ3GdPMkHRW1SJrIf8iHPECT/x/Aytf9iR1BKorvfrvfYWNo qjTgwzarh109kr3QBXtKH3JOxzohuLidwmOUU83JoD1wwRgX4ObI0YGr4jtEXNHA9j77 21Ew== X-Gm-Message-State: AGRZ1gILyRhAMKGcaordz25Ac0HDLKQQga7/xlXCJc8j6rueAd1zTgte /zu+wwW8IGClZjIdoUaLWtSQ4Kzseyc= X-Google-Smtp-Source: AJdET5cjG49Fue3JvYN+y53m9jBdFk7pJLQ+OFrzKescuSG02Q08AeQEP5aFjpji07o5CX5WacIQZg== X-Received: by 2002:a1c:1d12:: with SMTP id d18-v6mr2115254wmd.31.1540988488611; Wed, 31 Oct 2018 05:21:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 31 Oct 2018 12:21:18 +0000 Message-Id: <20181031122119.1669-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181031122119.1669-1-richard.henderson@linaro.org> References: <20181031122119.1669-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 09/10] cputlb: Filter flushes on already clean tlbs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Especially for guests with large numbers of tlbs, like ARM or PPC, we may well not use all of them in between flush operations. Remember which tlbs have been used since the last flush, and avoid any useless flushing. Tested-by: Emilio G. Cota Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 7 ++++++- accel/tcg/cputlb.c | 35 +++++++++++++++++++++++++---------- 2 files changed, 31 insertions(+), 11 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index c7b501d627..ca0fea8b27 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -166,7 +166,12 @@ typedef struct CPUTLBCommon { * mmu_idx may be discarded. Protected by tlb_c.lock. */ uint16_t pending_flush; - + /* + * Within dirty, for each bit N, modifications have been made to + * mmu_idx N since the last time that mmu_idx was flushed. + * Protected by tlb_c.lock. + */ + uint16_t dirty; /* * Statistics. These are not lock protected, but are read and * written atomically. This allows the monitor to print a snapshot diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e60628c350..f6c37bc4db 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -79,6 +79,9 @@ void tlb_init(CPUState *cpu) CPUArchState *env =3D cpu->env_ptr; =20 qemu_spin_init(&env->tlb_c.lock); + + /* Ensure that cpu_reset performs a full flush. */ + env->tlb_c.dirty =3D ALL_MMUIDX_BITS; } =20 /* flush_all_helper: run fn across all cpus @@ -129,31 +132,40 @@ static void tlb_flush_one_mmuidx_locked(CPUArchState = *env, int mmu_idx) static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data = data) { CPUArchState *env =3D cpu->env_ptr; - unsigned long mmu_idx_bitmask =3D data.host_int; - int mmu_idx; + uint16_t asked =3D data.host_int; + uint16_t all_dirty, work, to_clean; =20 assert_cpu_is_self(cpu); =20 - tlb_debug("mmu_idx:0x%04lx\n", mmu_idx_bitmask); + tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked); =20 qemu_spin_lock(&env->tlb_c.lock); - env->tlb_c.pending_flush &=3D ~mmu_idx_bitmask; =20 - for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - if (test_bit(mmu_idx, &mmu_idx_bitmask)) { - tlb_flush_one_mmuidx_locked(env, mmu_idx); - } + all_dirty =3D env->tlb_c.dirty; + to_clean =3D asked & all_dirty; + all_dirty &=3D ~to_clean; + env->tlb_c.dirty =3D all_dirty; + + for (work =3D to_clean; work !=3D 0; work &=3D work - 1) { + int mmu_idx =3D ctz32(work); + tlb_flush_one_mmuidx_locked(env, mmu_idx); } + qemu_spin_unlock(&env->tlb_c.lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 - if (mmu_idx_bitmask =3D=3D ALL_MMUIDX_BITS) { + if (to_clean =3D=3D ALL_MMUIDX_BITS) { atomic_set(&env->tlb_c.full_flush_count, env->tlb_c.full_flush_count + 1); } else { atomic_set(&env->tlb_c.part_flush_count, - env->tlb_c.part_flush_count + ctpop16(mmu_idx_bitmask)); + env->tlb_c.part_flush_count + ctpop16(to_clean)); + if (to_clean !=3D asked) { + atomic_set(&env->tlb_c.elide_flush_count, + env->tlb_c.elide_flush_count + + ctpop16(asked & ~to_clean)); + } } } =20 @@ -581,6 +593,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, */ qemu_spin_lock(&env->tlb_c.lock); =20 + /* Note that the tlb is no longer clean. */ + env->tlb_c.dirty |=3D 1 << mmu_idx; + /* Make sure there's no cached translation for the new page. */ tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); =20 --=20 2.17.2