From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540945901180134.39728746806645; Tue, 30 Oct 2018 17:31:41 -0700 (PDT) Received: from localhost ([::1]:56229 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeQ1-0001V6-RV for importer@patchew.org; Tue, 30 Oct 2018 20:31:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKb-0004mo-Rp for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:25:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKZ-00008d-Pr for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:25:57 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60372) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKZ-00008K-GC for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:25:55 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id E703C4FB68; Wed, 31 Oct 2018 01:23:19 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:15 -0400 Message-Id: <20181031002526.14262-2-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 01/13] qtest: Add set_irq_in command to set IRQ/GPIO level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Thomas Huth , Joel Stanley , Paolo Bonzini , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Adds a new qtest command "set_irq_in" which allows to set qemu gpio lines to a given level. Based on https://lists.gnu.org/archive/html/qemu-devel/2012-12/msg02363.html which never got merged. Signed-off-by: Steffen G=C3=B6rtz Originally-by: Matthew Ogilvie Reviewed-by: Stefan Hajnoczi --- qtest.c | 40 ++++++++++++++++++++++++++++++++++++++++ tests/libqtest.c | 10 ++++++++++ tests/libqtest.h | 28 ++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+) diff --git a/qtest.c b/qtest.c index 69b9e9962b..214f42a6c5 100644 --- a/qtest.c +++ b/qtest.c @@ -164,6 +164,14 @@ static bool qtest_opened; * where NUM is an IRQ number. For the PC, interrupts can be intercepted * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with * NUM=3D0 even though it is remapped to GSI 2). + * + * Setting interrupt level: + * + * > set_irq_in QOM-PATH IRQ LEVEL + * < OK + * + * Forcibly set the given interrupt pin to the given level. + * */ =20 static int hex2nib(char ch) @@ -326,7 +334,39 @@ static void qtest_process_command(CharBackend *chr, gc= har **words) irq_intercept_dev =3D dev; qtest_send_prefix(chr); qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "set_irq_in") =3D=3D 0) { + DeviceState *dev; + qemu_irq irq; + char *name; + int ret; + long num; + long level; =20 + g_assert(words[1] && words[2] && words[3] && words[4]); + + dev =3D DEVICE(object_resolve_path(words[1], NULL)); + if (!dev) { + qtest_send_prefix(chr); + qtest_send(chr, "FAIL Unknown device\n"); + return; + } + + if (strcmp(words[2], "unnamed-gpio-in") =3D=3D 0) { + name =3D NULL; + } else { + name =3D words[2]; + } + + ret =3D qemu_strtol(words[3], NULL, 10, &num); + g_assert(!ret); + ret =3D qemu_strtol(words[4], NULL, 10, &level); + g_assert(!ret); + + irq =3D qdev_get_gpio_in_named(dev, name, num); + + qemu_set_irq(irq, level); + qtest_send_prefix(chr); + qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "outb") =3D=3D 0 || strcmp(words[0], "outw") =3D=3D 0 || strcmp(words[0], "outl") =3D=3D 0) { diff --git a/tests/libqtest.c b/tests/libqtest.c index 44ce118cfc..1cbde0d91a 100644 --- a/tests/libqtest.c +++ b/tests/libqtest.c @@ -732,6 +732,16 @@ void qtest_irq_intercept_in(QTestState *s, const char = *qom_path) qtest_rsp(s, 0); } =20 +void qtest_set_irq_in(QTestState *s, const char *qom_path, const char *nam= e, + int num, int level) +{ + if (!name) { + name =3D "unnamed-gpio-in"; + } + qtest_sendf(s, "set_irq_in %s %s %d %d\n", qom_path, name, num, level); + qtest_rsp(s, 0); +} + static void qtest_out(QTestState *s, const char *cmd, uint16_t addr, uint3= 2_t value) { qtest_sendf(s, "%s 0x%x 0x%x\n", cmd, addr, value); diff --git a/tests/libqtest.h b/tests/libqtest.h index ed88ff99d5..65bffa9ace 100644 --- a/tests/libqtest.h +++ b/tests/libqtest.h @@ -232,6 +232,19 @@ void qtest_irq_intercept_in(QTestState *s, const char = *string); */ void qtest_irq_intercept_out(QTestState *s, const char *string); =20 +/** + * qtest_set_irq_in: + * @s: QTestState instance to operate on. + * @string: QOM path of a device + * @name: IRQ name + * @irq: IRQ number + * @level: IRQ level + * + * Force given device/irq GPIO-in pin to the given level. + */ +void qtest_set_irq_in(QTestState *s, const char *string, const char *name, + int irq, int level); + /** * qtest_outb: * @s: #QTestState instance to operate on. @@ -678,6 +691,21 @@ static inline void irq_intercept_out(const char *strin= g) qtest_irq_intercept_out(global_qtest, string); } =20 +/** + * qtest_set_irq_in: + * @string: QOM path of a device + * @name: IRQ name + * @irq: IRQ number + * @level: IRQ level + * + * Force given device/IRQ GPIO-in pin to the given level. + */ +static inline void set_irq_in(const char *string, const char *name, + int irq, int level) +{ + qtest_set_irq_in(global_qtest, string, name, irq, level); +} + /** * outb: * @addr: I/O port to write to. --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540945717286201.96130618759128; Tue, 30 Oct 2018 17:28:37 -0700 (PDT) Received: from localhost ([::1]:56212 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeN7-0007XQ-1H for importer@patchew.org; Tue, 30 Oct 2018 20:28:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKe-0004nJ-EL for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKd-0000AP-8c for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:00 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60380) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKa-00008p-Hg; Tue, 30 Oct 2018 20:25:56 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id A8C154FB6C; Wed, 31 Oct 2018 01:23:21 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:16 -0400 Message-Id: <20181031002526.14262-3-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 02/13] arm: Add header to host common definition for nRF51 SOC peripherals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , "open list:NRF51" , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Adds a header that provides definitions that are used across nRF51 peripherals Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi --- hw/arm/nrf51_soc.c | 33 ++++++++++----------------- include/hw/arm/nrf51.h | 44 ++++++++++++++++++++++++++++++++++++ include/hw/char/nrf51_uart.h | 1 - 3 files changed, 56 insertions(+), 22 deletions(-) create mode 100644 include/hw/arm/nrf51.h diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index b89c1bdea0..55f8eaafcb 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -21,27 +21,16 @@ #include "qemu/log.h" #include "cpu.h" =20 +#include "hw/arm/nrf51.h" #include "hw/arm/nrf51_soc.h" =20 -#define IOMEM_BASE 0x40000000 -#define IOMEM_SIZE 0x20000000 - -#define FICR_BASE 0x10000000 -#define FICR_SIZE 0x000000fc - -#define FLASH_BASE 0x00000000 -#define SRAM_BASE 0x20000000 - -#define PRIVATE_BASE 0xF0000000 -#define PRIVATE_SIZE 0x10000000 - /* * The size and base is for the NRF51822 part. If other parts * are supported in the future, add a sub-class of NRF51SoC for * the specific variants */ -#define NRF51822_FLASH_SIZE (256 * 1024) -#define NRF51822_SRAM_SIZE (16 * 1024) +#define NRF51822_FLASH_SIZE (256 * NRF51_PAGE_SIZE) +#define NRF51822_SRAM_SIZE (16 * NRF51_PAGE_SIZE) =20 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) =20 @@ -76,14 +65,14 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Err= or **errp) error_propagate(errp, err); return; } - memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); + memory_region_add_subregion(&s->container, NRF51_FLASH_BASE, &s->flash= ); =20 memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &er= r); if (err) { error_propagate(errp, err); return; } - memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); + memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); =20 /* UART */ object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); @@ -92,15 +81,17 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Err= or **errp) return; } mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); - memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0); + memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr= , 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, qdev_get_gpio_in(DEVICE(&s->cpu), - BASE_TO_IRQ(UART_BASE))); + BASE_TO_IRQ(NRF51_UART_BASE))); =20 - create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); - create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, + NRF51_IOMEM_SIZE); + create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, + NRF51_FICR_SIZE); create_unimplemented_device("nrf51_soc.private", - PRIVATE_BASE, PRIVATE_SIZE); + NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); } =20 static void nrf51_soc_init(Object *obj) diff --git a/include/hw/arm/nrf51.h b/include/hw/arm/nrf51.h new file mode 100644 index 0000000000..a89b6c23f0 --- /dev/null +++ b/include/hw/arm/nrf51.h @@ -0,0 +1,44 @@ +/* + * Nordic Semiconductor nRF51 Series SOC Common Defines + * + * This file hosts generic defines used in various nRF51 peripheral device= s. + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef NRF51_H +#define NRF51_H + +#define NRF51_FLASH_BASE 0x00000000 +#define NRF51_FICR_BASE 0x10000000 +#define NRF51_FICR_SIZE 0x00000100 +#define NRF51_UICR_BASE 0x10001000 +#define NRF51_SRAM_BASE 0x20000000 + +#define NRF51_IOMEM_BASE 0x40000000 +#define NRF51_IOMEM_SIZE 0x20000000 + +#define NRF51_UART_BASE 0x40002000 +#define NRF51_TIMER_BASE 0x40008000 +#define NRF51_RNG_BASE 0x4000D000 +#define NRF51_NVMC_BASE 0x4001E000 +#define NRF51_GPIO_BASE 0x50000000 + +#define NRF51_PRIVATE_BASE 0xF0000000 +#define NRF51_PRIVATE_SIZE 0x10000000 + +#define NRF51_PAGE_SIZE 1024 + +/* Trigger */ +#define NRF51_TRIGGER_TASK 0x01 + +/* Events */ +#define NRF51_EVENT_CLEAR 0x00 + +#endif diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h index e3ecb7c81c..eb1c15b490 100644 --- a/include/hw/char/nrf51_uart.h +++ b/include/hw/char/nrf51_uart.h @@ -16,7 +16,6 @@ #include "hw/registerfields.h" =20 #define UART_FIFO_LENGTH 6 -#define UART_BASE 0x40002000 #define UART_SIZE 0x1000 =20 #define TYPE_NRF51_UART "nrf51_soc.uart" --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540945702899728.2952508201748; Tue, 30 Oct 2018 17:28:22 -0700 (PDT) Received: from localhost ([::1]:56211 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeMt-0006Nx-51 for importer@patchew.org; Tue, 30 Oct 2018 20:28:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41503) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKe-0004n6-8v for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKc-00009t-C7 for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:00 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60396) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKc-00009P-0I for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:25:58 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id 2FFB74FB6F; Wed, 31 Oct 2018 01:23:23 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:17 -0400 Message-Id: <20181031002526.14262-4-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 03/13] hw/misc/nrf51_rng: Add NRF51 random number generator peripheral X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add a model of the NRF51 random number generator peripheral. This is a simple random generator that continuously generates new random values after startup. Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi --- hw/misc/Makefile.objs | 1 + hw/misc/nrf51_rng.c | 262 ++++++++++++++++++++++++++++++++++++ include/hw/misc/nrf51_rng.h | 83 ++++++++++++ 3 files changed, 346 insertions(+) create mode 100644 hw/misc/nrf51_rng.c create mode 100644 include/hw/misc/nrf51_rng.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 680350b3c3..04f3bfa516 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -74,3 +74,4 @@ obj-$(CONFIG_PVPANIC) +=3D pvpanic.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o +obj-$(CONFIG_NRF51_SOC) +=3D nrf51_rng.o diff --git a/hw/misc/nrf51_rng.c b/hw/misc/nrf51_rng.c new file mode 100644 index 0000000000..d188f044f4 --- /dev/null +++ b/hw/misc/nrf51_rng.c @@ -0,0 +1,262 @@ +/* + * nRF51 Random Number Generator + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.= pdf + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/arm/nrf51.h" +#include "hw/misc/nrf51_rng.h" +#include "crypto/random.h" + +static void update_irq(NRF51RNGState *s) +{ + bool irq =3D s->interrupt_enabled && s->event_valrdy; + qemu_set_irq(s->irq, irq); +} + +static uint64_t rng_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51RNGState *s =3D NRF51_RNG(opaque); + uint64_t r =3D 0; + + switch (offset) { + case NRF51_RNG_EVENT_VALRDY: + r =3D s->event_valrdy; + break; + case NRF51_RNG_REG_SHORTS: + r =3D s->shortcut_stop_on_valrdy; + break; + case NRF51_RNG_REG_INTEN: + case NRF51_RNG_REG_INTENSET: + case NRF51_RNG_REG_INTENCLR: + r =3D s->interrupt_enabled; + break; + case NRF51_RNG_REG_CONFIG: + r =3D s->filter_enabled; + break; + case NRF51_RNG_REG_VALUE: + r =3D s->value; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + return r; +} + +static int64_t calc_next_timeout(NRF51RNGState *s) +{ + int64_t timeout =3D qemu_clock_get_us(QEMU_CLOCK_VIRTUAL); + if (s->filter_enabled) { + timeout +=3D s->period_filtered_us; + } else { + timeout +=3D s->period_unfiltered_us; + } + + return timeout; +} + + +static void rng_update_timer(NRF51RNGState *s) +{ + if (s->active) { + timer_mod(&s->timer, calc_next_timeout(s)); + } else { + timer_del(&s->timer); + } +} + + +static void rng_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51RNGState *s =3D NRF51_RNG(opaque); + + switch (offset) { + case NRF51_RNG_TASK_START: + if (value =3D=3D NRF51_TRIGGER_TASK) { + s->active =3D 1; + rng_update_timer(s); + } + break; + case NRF51_RNG_TASK_STOP: + if (value =3D=3D NRF51_TRIGGER_TASK) { + s->active =3D 0; + rng_update_timer(s); + } + break; + case NRF51_RNG_EVENT_VALRDY: + if (value =3D=3D NRF51_EVENT_CLEAR) { + s->event_valrdy =3D 0; + } + break; + case NRF51_RNG_REG_SHORTS: + s->shortcut_stop_on_valrdy =3D + (value & BIT_MASK(NRF51_RNG_REG_SHORTS_VALRDY_STOP)) ? 1 := 0; + break; + case NRF51_RNG_REG_INTEN: + s->interrupt_enabled =3D + (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) ? 1 : 0; + break; + case NRF51_RNG_REG_INTENSET: + if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) { + s->interrupt_enabled =3D 1; + } + break; + case NRF51_RNG_REG_INTENCLR: + if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) { + s->interrupt_enabled =3D 0; + } + break; + case NRF51_RNG_REG_CONFIG: + s->filter_enabled =3D + (value & BIT_MASK(NRF51_RNG_REG_CONFIG_DECEN)) ? 1 := 0; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_irq(s); +} + +static const MemoryRegionOps rng_ops =3D { + .read =3D rng_read, + .write =3D rng_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4 +}; + +static void nrf51_rng_timer_expire(void *opaque) +{ + NRF51RNGState *s =3D NRF51_RNG(opaque); + + qcrypto_random_bytes(&s->value, 1, &error_abort); + + s->event_valrdy =3D 1; + qemu_set_irq(s->eep_valrdy, 1); + + if (s->shortcut_stop_on_valrdy) { + s->active =3D 0; + } + + rng_update_timer(s); + update_irq(s); +} + +static void nrf51_rng_tep_start(void *opaque, int n, int level) +{ + NRF51RNGState *s =3D NRF51_RNG(opaque); + + if (level) { + s->active =3D 1; + rng_update_timer(s); + } +} + +static void nrf51_rng_tep_stop(void *opaque, int n, int level) +{ + NRF51RNGState *s =3D NRF51_RNG(opaque); + + if (level) { + s->active =3D 0; + rng_update_timer(s); + } +} + + +static void nrf51_rng_init(Object *obj) +{ + NRF51RNGState *s =3D NRF51_RNG(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->mmio, obj, &rng_ops, s, + TYPE_NRF51_RNG, NRF51_RNG_SIZE); + sysbus_init_mmio(sbd, &s->mmio); + + timer_init_us(&s->timer, QEMU_CLOCK_VIRTUAL, nrf51_rng_timer_expire, s= ); + + sysbus_init_irq(sbd, &s->irq); + + /* Tasks */ + qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_start, "tep_start", 1= ); + qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_stop, "tep_stop", 1); + + /* Events */ + qdev_init_gpio_out_named(DEVICE(s), &s->eep_valrdy, "eep_valrdy", 1); +} + +static void nrf51_rng_reset(DeviceState *dev) +{ + NRF51RNGState *s =3D NRF51_RNG(dev); + + s->value =3D 0; + s->active =3D 0; + s->event_valrdy =3D 0; + s->shortcut_stop_on_valrdy =3D 0; + s->interrupt_enabled =3D 0; + s->filter_enabled =3D 0; + + rng_update_timer(s); +} + + +static Property nrf51_rng_properties[] =3D { + DEFINE_PROP_UINT16("period_unfiltered_us", NRF51RNGState, + period_unfiltered_us, 167), + DEFINE_PROP_UINT16("period_filtered_us", NRF51RNGState, + period_filtered_us, 660), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_rng =3D { + .name =3D "nrf51_soc.rng", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(active, NRF51RNGState), + VMSTATE_UINT32(event_valrdy, NRF51RNGState), + VMSTATE_UINT32(shortcut_stop_on_valrdy, NRF51RNGState), + VMSTATE_UINT32(interrupt_enabled, NRF51RNGState), + VMSTATE_UINT32(filter_enabled, NRF51RNGState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_rng_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D nrf51_rng_properties; + dc->vmsd =3D &vmstate_rng; + dc->reset =3D nrf51_rng_reset; +} + +static const TypeInfo nrf51_rng_info =3D { + .name =3D TYPE_NRF51_RNG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51RNGState), + .instance_init =3D nrf51_rng_init, + .class_init =3D nrf51_rng_class_init +}; + +static void nrf51_rng_register_types(void) +{ + type_register_static(&nrf51_rng_info); +} + +type_init(nrf51_rng_register_types) diff --git a/include/hw/misc/nrf51_rng.h b/include/hw/misc/nrf51_rng.h new file mode 100644 index 0000000000..3d6bf79997 --- /dev/null +++ b/include/hw/misc/nrf51_rng.h @@ -0,0 +1,83 @@ +/* + * nRF51 Random Number Generator + * + * QEMU interface: + * + Property "period_unfiltered_us": Time between two biased values in + * microseconds. + * + Property "period_filtered_us": Time between two unbiased values in + * microseconds. + * + sysbus MMIO regions 0: Memory Region with tasks, events and registers + * to be mapped to the peripherals instance address by the SOC. + * + Named GPIO output "irq": Interrupt line of the peripheral. Must be + * connected to the associated peripheral interrupt line of the NVIC. + * + Named GPIO output "eep_valrdy": Event set when new random value is re= ady + * to be read. + * + Named GPIO input "tep_start": Task that triggers start of continuous + * generation of random values. + * + Named GPIO input "tep_stop": Task that ends continuous generation of + * random values. + * + * Accuracy of the peripheral model: + * + Stochastic properties of different configurations of the random source + * are not modeled. + * + Generation of unfiltered and filtered random values take at least the + * average generation time stated in the production specification; + * non-deterministic generation times are not modeled. + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + */ +#ifndef NRF51_RNG_H +#define NRF51_RNG_H + +#include "hw/sysbus.h" +#include "qemu/timer.h" +#define TYPE_NRF51_RNG "nrf51_soc.rng" +#define NRF51_RNG(obj) OBJECT_CHECK(NRF51RNGState, (obj), TYPE_NRF51_RNG) + +#define NRF51_RNG_SIZE 0x1000 + +#define NRF51_RNG_TASK_START 0x000 +#define NRF51_RNG_TASK_STOP 0x004 +#define NRF51_RNG_EVENT_VALRDY 0x100 +#define NRF51_RNG_REG_SHORTS 0x200 +#define NRF51_RNG_REG_SHORTS_VALRDY_STOP 0 +#define NRF51_RNG_REG_INTEN 0x300 +#define NRF51_RNG_REG_INTEN_VALRDY 0 +#define NRF51_RNG_REG_INTENSET 0x304 +#define NRF51_RNG_REG_INTENCLR 0x308 +#define NRF51_RNG_REG_CONFIG 0x504 +#define NRF51_RNG_REG_CONFIG_DECEN 0 +#define NRF51_RNG_REG_VALUE 0x508 + +typedef struct { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq irq; + + /* Event End Points */ + qemu_irq eep_valrdy; + + QEMUTimer timer; + + /* Time between generation of successive unfiltered values in us */ + uint16_t period_unfiltered_us; + /* Time between generation of successive filtered values in us */ + uint16_t period_filtered_us; + + uint8_t value; + + uint32_t active; + uint32_t event_valrdy; + uint32_t shortcut_stop_on_valrdy; + uint32_t interrupt_enabled; + uint32_t filter_enabled; + +} NRF51RNGState; + + +#endif /* NRF51_RNG_H_ */ --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540945912429253.8372005732798; Tue, 30 Oct 2018 17:31:52 -0700 (PDT) Received: from localhost ([::1]:56230 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeQD-0001Zu-8R for importer@patchew.org; Tue, 30 Oct 2018 20:31:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41534) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKg-0004on-DY for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKf-0000Bx-JH for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:02 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60408) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKd-0000AV-Hd; Tue, 30 Oct 2018 20:25:59 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id 8DAC14FB6E; Wed, 31 Oct 2018 01:23:24 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:18 -0400 Message-Id: <20181031002526.14262-5-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 04/13] arm: Instantiate NRF51 random number generator X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , "open list:NRF51" , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Use RNG in SOC. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi --- hw/arm/nrf51_soc.c | 16 ++++++++++++++++ include/hw/arm/nrf51_soc.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 55f8eaafcb..d2a19b8ead 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -86,6 +86,19 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Erro= r **errp) qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_UART_BASE))); =20 + /* RNG */ + object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr,= 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(NRF51_RNG_BASE))); + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, @@ -110,6 +123,9 @@ static void nrf51_soc_init(Object *obj) TYPE_NRF51_UART); object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", &error_abort); + + sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), + TYPE_NRF51_RNG); } =20 static Property nrf51_soc_properties[] =3D { diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 73fc92e9a8..9e3ba916bd 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -13,6 +13,7 @@ #include "hw/sysbus.h" #include "hw/arm/armv7m.h" #include "hw/char/nrf51_uart.h" +#include "hw/misc/nrf51_rng.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ @@ -26,6 +27,7 @@ typedef struct NRF51State { ARMv7MState cpu; =20 NRF51UARTState uart; + NRF51RNGState rng; =20 MemoryRegion iomem; MemoryRegion sram; --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540946118133426.6971175708362; Tue, 30 Oct 2018 17:35:18 -0700 (PDT) Received: from localhost ([::1]:56246 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeTT-0005OF-K7 for importer@patchew.org; Tue, 30 Oct 2018 20:35:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41541) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKg-0004p8-Rr for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKf-0000Bh-5f for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:02 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60412) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKe-0000BR-Rf for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:01 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id 176DA4FB6B; Wed, 31 Oct 2018 01:23:25 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:19 -0400 Message-Id: <20181031002526.14262-6-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 05/13] hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The nRF51 contains three regions of non-volatile memory (NVM): - CODE (R/W): contains code - FICR (R): Factory information like code size, chip id etc. - UICR (R/W): Changeable configuration data. Lock bits, Code protection configuration, Bootloader address, Nordic SoftRadio configuration, Firmware configuration. Read and write access to the memories is managed by the Non-volatile memory controller. Memory schema: [ CPU ] -+- [ NVM, either FICR, UICR or CODE ] | | \- [ NVMC ] Signed-off-by: Steffen G=C3=B6rtz --- hw/nvram/Makefile.objs | 1 + hw/nvram/nrf51_nvm.c | 339 +++++++++++++++++++++++++++++++++++ include/hw/nvram/nrf51_nvm.h | 70 ++++++++ 3 files changed, 410 insertions(+) create mode 100644 hw/nvram/nrf51_nvm.c create mode 100644 include/hw/nvram/nrf51_nvm.h diff --git a/hw/nvram/Makefile.objs b/hw/nvram/Makefile.objs index a912d25391..3f978e6212 100644 --- a/hw/nvram/Makefile.objs +++ b/hw/nvram/Makefile.objs @@ -5,3 +5,4 @@ common-obj-y +=3D fw_cfg.o common-obj-y +=3D chrp_nvram.o common-obj-$(CONFIG_MAC_NVRAM) +=3D mac_nvram.o obj-$(CONFIG_PSERIES) +=3D spapr_nvram.o +obj-$(CONFIG_NRF51_SOC) +=3D nrf51_nvm.o diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c new file mode 100644 index 0000000000..078072f031 --- /dev/null +++ b/hw/nvram/nrf51_nvm.c @@ -0,0 +1,339 @@ +/* + * Nordic Semiconductor nRF51 non-volatile memory + * + * It provides an interface to erase regions in flash memory. + * Furthermore it provides the user and factory information registers. + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * + * See nRF51 reference manual and product sheet sections: + * + Non-Volatile Memory Controller (NVMC) + * + Factory Information Configuration Registers (FICR) + * + User Information Configuration Registers (UICR) + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "exec/address-spaces.h" +#include "hw/arm/nrf51.h" +#include "hw/nvram/nrf51_nvm.h" + +/* FICR Registers Assignments + * CODEPAGESIZE 0x010 + * CODESIZE 0x014 + * CLENR0 0x028 + * PPFC 0x02C + * NUMRAMBLOCK 0x034 + * SIZERAMBLOCKS 0x038 + * SIZERAMBLOCK[0] 0x038 + * SIZERAMBLOCK[1] 0x03C + * SIZERAMBLOCK[2] 0x040 + * SIZERAMBLOCK[3] 0x044 + * CONFIGID 0x05C + * DEVICEID[0] 0x060 + * DEVICEID[1] 0x064 + * ER[0] 0x080 + * ER[1] 0x084 + * ER[2] 0x088 + * ER[3] 0x08C + * IR[0] 0x090 + * IR[1] 0x094 + * IR[2] 0x098 + * IR[3] 0x09C + * DEVICEADDRTYPE 0x0A0 + * DEVICEADDR[0] 0x0A4 + * DEVICEADDR[1] 0x0A8 + * OVERRIDEEN 0x0AC + * NRF_1MBIT[0] 0x0B0 + * NRF_1MBIT[1] 0x0B4 + * NRF_1MBIT[2] 0x0B8 + * NRF_1MBIT[3] 0x0BC + * NRF_1MBIT[4] 0x0C0 + * BLE_1MBIT[0] 0x0EC + * BLE_1MBIT[1] 0x0F0 + * BLE_1MBIT[2] 0x0F4 + * BLE_1MBIT[3] 0x0F8 + * BLE_1MBIT[4] 0x0FC + */ +static const uint32_t ficr_content[64] =3D { + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000400, + 0x00000100, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000002, 0x00002000, + 0x00002000, 0x00002000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000003, + 0x12345678, 0x9ABCDEF1, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF +}; + +static uint64_t ficr_read(void *opaque, hwaddr offset, unsigned int size) +{ + assert(offset <=3D sizeof(ficr_content)); + return ficr_content[offset / 4]; +} + +static void ficr_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int size) +{ + /* Intentionally do nothing */ +} + +static const MemoryRegionOps ficr_ops =3D { + .read =3D ficr_read, + .write =3D ficr_write, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .impl.unaligned =3D false, +}; + +/* UICR Registers Assignments + * CLENR0 0x000 + * RBPCONF 0x004 + * XTALFREQ 0x008 + * FWID 0x010 + * BOOTLOADERADDR 0x014 + * NRFFW[0] 0x014 + * NRFFW[1] 0x018 + * NRFFW[2] 0x01C + * NRFFW[3] 0x020 + * NRFFW[4] 0x024 + * NRFFW[5] 0x028 + * NRFFW[6] 0x02C + * NRFFW[7] 0x030 + * NRFFW[8] 0x034 + * NRFFW[9] 0x038 + * NRFFW[10] 0x03C + * NRFFW[11] 0x040 + * NRFFW[12] 0x044 + * NRFFW[13] 0x048 + * NRFFW[14] 0x04C + * NRFHW[0] 0x050 + * NRFHW[1] 0x054 + * NRFHW[2] 0x058 + * NRFHW[3] 0x05C + * NRFHW[4] 0x060 + * NRFHW[5] 0x064 + * NRFHW[6] 0x068 + * NRFHW[7] 0x06C + * NRFHW[8] 0x070 + * NRFHW[9] 0x074 + * NRFHW[10] 0x078 + * NRFHW[11] 0x07C + * CUSTOMER[0] 0x080 + * CUSTOMER[1] 0x084 + * CUSTOMER[2] 0x088 + * CUSTOMER[3] 0x08C + * CUSTOMER[4] 0x090 + * CUSTOMER[5] 0x094 + * CUSTOMER[6] 0x098 + * CUSTOMER[7] 0x09C + * CUSTOMER[8] 0x0A0 + * CUSTOMER[9] 0x0A4 + * CUSTOMER[10] 0x0A8 + * CUSTOMER[11] 0x0AC + * CUSTOMER[12] 0x0B0 + * CUSTOMER[13] 0x0B4 + * CUSTOMER[14] 0x0B8 + * CUSTOMER[15] 0x0BC + * CUSTOMER[16] 0x0C0 + * CUSTOMER[17] 0x0C4 + * CUSTOMER[18] 0x0C8 + * CUSTOMER[19] 0x0CC + * CUSTOMER[20] 0x0D0 + * CUSTOMER[21] 0x0D4 + * CUSTOMER[22] 0x0D8 + * CUSTOMER[23] 0x0DC + * CUSTOMER[24] 0x0E0 + * CUSTOMER[25] 0x0E4 + * CUSTOMER[26] 0x0E8 + * CUSTOMER[27] 0x0EC + * CUSTOMER[28] 0x0F0 + * CUSTOMER[29] 0x0F4 + * CUSTOMER[30] 0x0F8 + * CUSTOMER[31] 0x0FC + */ + +static uint64_t uicr_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51NVMState *s =3D NRF51_NVM(opaque); + + assert(offset <=3D sizeof(s->uicr_content)); + return s->uicr_content[offset / 4]; +} + +static void uicr_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int size) +{ + NRF51NVMState *s =3D NRF51_NVM(opaque); + + s->uicr_content[offset / 4] =3D value; +} + +static const MemoryRegionOps uicr_ops =3D { + .read =3D uicr_read, + .write =3D uicr_write, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .impl.unaligned =3D false, +}; + + +static uint64_t io_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51NVMState *s =3D NRF51_NVM(opaque); + uint64_t r =3D 0; + + switch (offset) { + case NRF51_NVMC_READY: + r =3D NRF51_NVMC_READY_READY; + break; + case NRF51_NVMC_CONFIG: + r =3D s->config; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", __func__, offs= et); + break; + } + + return r; +} + +static void io_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int size) +{ + NRF51NVMState *s =3D NRF51_NVM(opaque); + + switch (offset) { + case NRF51_NVMC_CONFIG: + s->config =3D value & NRF51_NVMC_CONFIG_MASK; + break; + case NRF51_NVMC_ERASEPCR0: + case NRF51_NVMC_ERASEPCR1: + value &=3D ~(NRF51_PAGE_SIZE - 1); + if (value < (s->code_size * NRF51_PAGE_SIZE)) { + address_space_write(&s->as, value, MEMTXATTRS_UNSPECIFIED, + s->empty_page, NRF51_PAGE_SIZE); + } + break; + case NRF51_NVMC_ERASEALL: + if (value =3D=3D NRF51_NVMC_ERASE) { + for (uint32_t i =3D 0; i < s->code_size; i++) { + address_space_write(&s->as, i * NRF51_PAGE_SIZE, + MEMTXATTRS_UNSPECIFIED, s->empty_page, NRF51_PAGE_SIZE); + } + memset(s->uicr_content, 0xFF, sizeof(s->uicr_content)); + } + break; + case NRF51_NVMC_ERASEUICR: + if (value =3D=3D NRF51_NVMC_ERASE) { + memset(s->uicr_content, 0xFF, sizeof(s->uicr_content)); + } + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", __func__, off= set); + } +} + +static const MemoryRegionOps io_ops =3D { + .read =3D io_read, + .write =3D io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void nrf51_nvm_init(Object *obj) +{ + NRF51NVMState *s =3D NRF51_NVM(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->mmio, obj, &io_ops, s, "nrf51_soc.nvmc", + NRF51_NVMC_SIZE); + sysbus_init_mmio(sbd, &s->mmio); + + memory_region_init_io(&s->ficr, NULL, &ficr_ops, s, "nrf51_soc.ficr", + sizeof(ficr_content)); + sysbus_init_mmio(sbd, &s->ficr); + + memory_region_init_io(&s->uicr, NULL, &uicr_ops, s, "nrf51_soc.uicr", + sizeof(s->uicr_content)); + sysbus_init_mmio(sbd, &s->uicr); +} + +static void nrf51_nvm_realize(DeviceState *dev, Error **errp) +{ + NRF51NVMState *s =3D NRF51_NVM(dev); + + if (!s->mr) { + error_setg(errp, "memory property was not set"); + return; + } + + s->empty_page =3D g_malloc(NRF51_PAGE_SIZE); + memset(s->empty_page, 0xFF, NRF51_PAGE_SIZE); + + address_space_init(&s->as, s->mr, "system-memory"); +} + +static void nrf51_nvm_reset(DeviceState *dev) +{ + NRF51NVMState *s =3D NRF51_NVM(dev); + + memset(s->uicr_content, '\0', sizeof(s->uicr_content)); +} + +static Property nrf51_nvm_properties[] =3D { + DEFINE_PROP_UINT32("code_size", NRF51NVMState, code_size, 0x100), + DEFINE_PROP_LINK("memory", NRF51NVMState, mr, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_nvm =3D { + .name =3D "nrf51_soc.nvm", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(uicr_content, NRF51NVMState, + NRF51_UICR_FIXTURE_SIZE), + VMSTATE_UINT32(config, NRF51NVMState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_nvm_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D nrf51_nvm_properties; + dc->vmsd =3D &vmstate_nvm; + dc->realize =3D nrf51_nvm_realize; + dc->reset =3D nrf51_nvm_reset; +} + +static const TypeInfo nrf51_nvm_info =3D { + .name =3D TYPE_NRF51_NVM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51NVMState), + .instance_init =3D nrf51_nvm_init, + .class_init =3D nrf51_nvm_class_init +}; + +static void nrf51_nvm_register_types(void) +{ + type_register_static(&nrf51_nvm_info); +} + +type_init(nrf51_nvm_register_types) diff --git a/include/hw/nvram/nrf51_nvm.h b/include/hw/nvram/nrf51_nvm.h new file mode 100644 index 0000000000..df55e4027a --- /dev/null +++ b/include/hw/nvram/nrf51_nvm.h @@ -0,0 +1,70 @@ +/* + * Nordic Semiconductor nRF51 non-volatile memory + * + * It provides an interface to erase regions in flash memory. + * Furthermore it provides the user and factory information registers. + * + * QEMU interface: + * + sysbus MMIO regions 0: NVMC peripheral registers + * + sysbus MMIO regions 1: FICR peripheral registers + * + sysbus MMIO regions 2: UICR peripheral registers + * + code_size property to set the code size in number of pages. + * + * Accuracy of the peripheral model: + * + The NVMC is always ready, all requested erase operations succeed + * immediately. + * + CONFIG.WEN and CONFIG.EEN flags can be written and read back + * but are not evaluated to check whether a requested write/erase operat= ion + * is legal. + * + Code regions (MPU configuration) are disregarded. + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + */ +#ifndef NRF51_NVM_H +#define NRF51_NVM_H + +#include "hw/sysbus.h" +#define TYPE_NRF51_NVM "nrf51_soc.nvm" +#define NRF51_NVM(obj) OBJECT_CHECK(NRF51NVMState, (obj), TYPE_NRF51_NVM) + +#define NRF51_UICR_FIXTURE_SIZE 64 + +#define NRF51_NVMC_SIZE 0x1000 + +#define NRF51_NVMC_READY 0x400 +#define NRF51_NVMC_READY_READY 0x01 +#define NRF51_NVMC_CONFIG 0x504 +#define NRF51_NVMC_CONFIG_MASK 0x03 +#define NRF51_NVMC_CONFIG_WEN 0x01 +#define NRF51_NVMC_CONFIG_EEN 0x02 +#define NRF51_NVMC_ERASEPCR1 0x508 +#define NRF51_NVMC_ERASEPCR0 0x510 +#define NRF51_NVMC_ERASEALL 0x50C +#define NRF51_NVMC_ERASEUICR 0x514 +#define NRF51_NVMC_ERASE 0x01 + +#define NRF51_UICR_SIZE 0x100 + +typedef struct NRF51NVMState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + MemoryRegion ficr; + MemoryRegion uicr; + + uint32_t uicr_content[NRF51_UICR_FIXTURE_SIZE]; + uint32_t code_size; + uint8_t *empty_page; + MemoryRegion *mr; + AddressSpace as; + + uint32_t config; + +} NRF51NVMState; + + +#endif --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540946118948495.5233083050132; Tue, 30 Oct 2018 17:35:18 -0700 (PDT) Received: from localhost ([::1]:56247 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeTY-0005Ss-Ot for importer@patchew.org; Tue, 30 Oct 2018 20:35:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41601) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKl-0004sp-B6 for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKk-0000Ex-8m for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:07 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60428) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKg-0000C9-Cl; Tue, 30 Oct 2018 20:26:02 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id 7E5584FB6E; Wed, 31 Oct 2018 01:23:27 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:20 -0400 Message-Id: <20181031002526.14262-7-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 06/13] arm: Instantiate NRF51 special NVM's and NVMC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , "open list:NRF51" , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Instantiates UICR, FICR and NVMC in nRF51 SOC. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi --- hw/arm/nrf51_soc.c | 37 ++++++++++++++++++++++++++++++++++--- include/hw/arm/nrf51_soc.h | 2 ++ 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index d2a19b8ead..fd0efd0ee8 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -29,7 +29,8 @@ * are supported in the future, add a sub-class of NRF51SoC for * the specific variants */ -#define NRF51822_FLASH_SIZE (256 * NRF51_PAGE_SIZE) +#define NRF51822_FLASH_PAGES 256 +#define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) #define NRF51822_SRAM_SIZE (16 * NRF51_PAGE_SIZE) =20 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) @@ -99,10 +100,37 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Er= ror **errp) qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_RNG_BASE))); =20 + /* UICR, FICR, NVMC */ + object_property_set_link(OBJECT(&s->nvm), OBJECT(&s->container), "memo= ry", + &err); + if (err) { + error_propagate(errp, err); + return; + } + + object_property_set_uint(OBJECT(&s->nvm), NRF51822_FLASH_PAGES, "code_= size", + &err); + if (err) { + error_propagate(errp, err); + return; + } + + object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr= , 0); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); + memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr= , 0); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); + memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr= , 0); + + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); - create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, - NRF51_FICR_SIZE); create_unimplemented_device("nrf51_soc.private", NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); } @@ -126,6 +154,9 @@ static void nrf51_soc_init(Object *obj) =20 sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), TYPE_NRF51_RNG); + + sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_= NVM); + } =20 static Property nrf51_soc_properties[] =3D { diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 9e3ba916bd..c3f4d5bcdc 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -14,6 +14,7 @@ #include "hw/arm/armv7m.h" #include "hw/char/nrf51_uart.h" #include "hw/misc/nrf51_rng.h" +#include "hw/nvram/nrf51_nvm.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ @@ -28,6 +29,7 @@ typedef struct NRF51State { =20 NRF51UARTState uart; NRF51RNGState rng; + NRF51NVMState nvm; =20 MemoryRegion iomem; MemoryRegion sram; --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540945912196703.9357164843485; Tue, 30 Oct 2018 17:31:52 -0700 (PDT) Received: from localhost ([::1]:56232 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeQH-0001d3-53 for importer@patchew.org; Tue, 30 Oct 2018 20:31:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41580) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKk-0004sR-5n for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKi-0000Dz-H8 for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:06 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60440) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKi-0000DY-5x for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:04 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id 060CE4FB72; Wed, 31 Oct 2018 01:23:28 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:21 -0400 Message-Id: <20181031002526.14262-8-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 07/13] tests: Add bbc:microbit / nRF51 test suite X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Thomas Huth , Joel Stanley , Paolo Bonzini , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The microbit-test includes tests for the nRF51 NVMC peripheral and will host future nRF51 peripheral tests and board-level bbc:microbit tests. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi --- tests/Makefile.include | 2 + tests/microbit-test.c | 117 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 tests/microbit-test.c diff --git a/tests/Makefile.include b/tests/Makefile.include index f77a495109..602346eeed 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -274,6 +274,7 @@ check-qtest-sparc64-y +=3D tests/boot-serial-test$(EXES= UF) check-qtest-arm-y +=3D tests/tmp105-test$(EXESUF) check-qtest-arm-y +=3D tests/pca9552-test$(EXESUF) check-qtest-arm-y +=3D tests/ds1338-test$(EXESUF) +check-qtest-arm-y +=3D tests/microbit-test$(EXESUF) check-qtest-arm-y +=3D tests/m25p80-test$(EXESUF) check-qtest-arm-y +=3D tests/virtio-blk-test$(EXESUF) check-qtest-arm-y +=3D tests/test-arm-mptimer$(EXESUF) @@ -695,6 +696,7 @@ tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-se= ctor.o $(libqos-obj-y) tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) tests/pca9552-test$(EXESUF): tests/pca9552-test.o $(libqos-omap-obj-y) tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/microbit-test$(EXESUF): tests/microbit-test.o tests/m25p80-test$(EXESUF): tests/m25p80-test.o tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) diff --git a/tests/microbit-test.c b/tests/microbit-test.c new file mode 100644 index 0000000000..981a36ed82 --- /dev/null +++ b/tests/microbit-test.c @@ -0,0 +1,117 @@ + /* + * QTest testcase for Microbit board using the Nordic Semiconductor nRF51 = SoC. + * + * nRF51: + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Microbit Board: http://microbit.org/ + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + + +#include "qemu/osdep.h" +#include "exec/hwaddr.h" +#include "libqtest.h" + +#include "hw/arm/nrf51.h" +#include "hw/nvram/nrf51_nvm.h" + +#define FLASH_SIZE (256 * NRF51_PAGE_SIZE) + +static void fill_and_erase(hwaddr base, hwaddr size, uint32_t address_reg) +{ + /* Fill memory */ + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); + for (hwaddr i =3D 0; i < size; ++i) { + writeb(base + i, i); + g_assert_cmpuint(readb(base + i), =3D=3D, i & 0xFF); + } + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + /* Erase Page */ + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + writel(NRF51_NVMC_BASE + address_reg, base); + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + /* Check memory */ + for (hwaddr i =3D 0; i < size; ++i) { + g_assert_cmpuint(readb(base + i), =3D=3D, 0xFF); + } +} + +static void test_nrf51_nvmc(void) +{ + uint32_t value; + /* Test always ready */ + value =3D readl(NRF51_NVMC_BASE + NRF51_NVMC_READY); + g_assert_cmpuint(value & 0x01, =3D=3D, 0x01); + + /* Test write-read config register */ + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x03); + g_assert_cmpuint(readl(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG), =3D=3D, 0= x03); + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + g_assert_cmpuint(readl(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG), =3D=3D, 0= x00); + + /* Test PCR0 */ + fill_and_erase(NRF51_FLASH_BASE, NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR0= ); + fill_and_erase(NRF51_FLASH_BASE + NRF51_PAGE_SIZE, + NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR0); + + /* Test PCR1 */ + fill_and_erase(NRF51_FLASH_BASE, NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR1= ); + fill_and_erase(NRF51_FLASH_BASE + NRF51_PAGE_SIZE, + NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR1); + + /* Erase all */ + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); + for (hwaddr i =3D 0; i < FLASH_SIZE / 4; i++) { + writel(NRF51_FLASH_BASE + i * 4, i); + g_assert_cmpuint(readl(NRF51_FLASH_BASE + i * 4), =3D=3D, i); + } + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + writel(NRF51_NVMC_BASE + NRF51_NVMC_ERASEALL, 0x01); + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + for (hwaddr i =3D 0; i < FLASH_SIZE / 4; i++) { + g_assert_cmpuint(readl(NRF51_FLASH_BASE + i * 4), =3D=3D, 0xFFFFFF= FF); + } + + /* Erase UICR */ + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); + for (hwaddr i =3D 0; i < NRF51_UICR_SIZE / 4; i++) { + writel(NRF51_UICR_BASE + i * 4, i); + g_assert_cmpuint(readl(NRF51_UICR_BASE + i * 4), =3D=3D, i); + } + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + writel(NRF51_NVMC_BASE + NRF51_NVMC_ERASEUICR, 0x01); + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + for (hwaddr i =3D 0; i < NRF51_UICR_SIZE / 4; i++) { + g_assert_cmpuint(readl(NRF51_UICR_BASE + i * 4), =3D=3D, 0xFFFFFFF= F); + } +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + + global_qtest =3D qtest_initf("-machine microbit"); + + qtest_add_func("/microbit/nrf51/nvmc", test_nrf51_nvmc); + + ret =3D g_test_run(); + + qtest_quit(global_qtest); + return ret; +} --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154094616367945.2880177799417; Tue, 30 Oct 2018 17:36:03 -0700 (PDT) Received: from localhost ([::1]:56256 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeUM-00066o-8r for importer@patchew.org; Tue, 30 Oct 2018 20:36:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41604) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKl-0004sq-LI for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKj-0000Ec-RW for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:07 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60454) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKj-0000EQ-HE for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:05 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id C0B634FB6E; Wed, 31 Oct 2018 01:23:30 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:22 -0400 Message-Id: <20181031002526.14262-9-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 08/13] hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheral X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This adds a model of the nRF51 GPIO peripheral. Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf The nRF51 series microcontrollers support up to 32 GPIO pins in various con= figurations. The pins can be used as input pins with pull-ups or pull-down. Furthermore, three different output driver modes per level are available (disconnected, standard, high-current). The GPIO-Peripheral has a mechanism for detecting level changes which is not featured in this model. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Stefan Hajnoczi --- Makefile.objs | 1 + hw/gpio/Makefile.objs | 1 + hw/gpio/nrf51_gpio.c | 292 +++++++++++++++++++++++++++++++++++ hw/gpio/trace-events | 7 + include/hw/gpio/nrf51_gpio.h | 69 +++++++++ 5 files changed, 370 insertions(+) create mode 100644 hw/gpio/nrf51_gpio.c create mode 100644 hw/gpio/trace-events create mode 100644 include/hw/gpio/nrf51_gpio.h diff --git a/Makefile.objs b/Makefile.objs index 1e1ff387d7..fbc3bad1e1 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -243,6 +243,7 @@ trace-events-subdirs +=3D hw/vfio trace-events-subdirs +=3D hw/virtio trace-events-subdirs +=3D hw/watchdog trace-events-subdirs +=3D hw/xen +trace-events-subdirs +=3D hw/gpio trace-events-subdirs +=3D io trace-events-subdirs +=3D linux-user trace-events-subdirs +=3D migration diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs index fa0a72e6d0..e5da0cb54f 100644 --- a/hw/gpio/Makefile.objs +++ b/hw/gpio/Makefile.objs @@ -8,3 +8,4 @@ common-obj-$(CONFIG_GPIO_KEY) +=3D gpio_key.o obj-$(CONFIG_OMAP) +=3D omap_gpio.o obj-$(CONFIG_IMX) +=3D imx_gpio.o obj-$(CONFIG_RASPI) +=3D bcm2835_gpio.o +obj-$(CONFIG_NRF51_SOC) +=3D nrf51_gpio.o diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c new file mode 100644 index 0000000000..53f5036015 --- /dev/null +++ b/hw/gpio/nrf51_gpio.c @@ -0,0 +1,292 @@ +/* + * nRF51 System-on-Chip general purpose input/output register definition + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/gpio/nrf51_gpio.h" +#include "trace.h" + +/* + * Check if the output driver is connected to the direction switch + * given the current configuration and logic level. + * It is not differentiated between standard and "high"(-power) drive mode= s. + */ +static bool is_connected(uint32_t config, uint32_t level) +{ + bool state; + uint32_t drive_config =3D extract32(config, 8, 3); + + switch (drive_config) { + case 0 ... 3: + state =3D true; + break; + case 4 ... 5: + state =3D level !=3D 0; + break; + case 6 ... 7: + state =3D level =3D=3D 0; + break; + } + + return state; +} + +static void update_output_irq(NRF51GPIOState *s, size_t i, + bool connected, bool level) +{ + int64_t irq_level =3D connected ? level : -1; + bool old_connected =3D extract32(s->old_out_connected, i, 1); + bool old_level =3D extract32(s->old_out, i, 1); + + if ((old_connected !=3D connected) || (old_level !=3D level)) { + qemu_set_irq(s->output[i], irq_level); + trace_nrf51_gpio_update_output_irq(i, irq_level); + } + + s->old_out =3D deposit32(s->old_out, i, 1, level); + s->old_out_connected =3D deposit32(s->old_out_connected, i, 1, connect= ed); +} + +static void update_state(NRF51GPIOState *s) +{ + uint32_t pull; + bool connected_out, dir, connected_in, out, input; + + for (size_t i =3D 0; i < NRF51_GPIO_PINS; i++) { + pull =3D extract32(s->cnf[i], 2, 2); + dir =3D extract32(s->cnf[i], 0, 1); + connected_in =3D extract32(s->in_mask, i, 1); + out =3D extract32(s->out, i, 1); + input =3D !extract32(s->cnf[i], 1, 1); + connected_out =3D is_connected(s->cnf[i], out) && dir; + + update_output_irq(s, i, connected_out, out); + + /* Pin both driven externally and internally */ + if (connected_out && connected_in) { + qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n= ", i); + } + + /* + * Input buffer disconnected from internal/external drives, so + * pull-up/pull-down becomes relevant + */ + if (!input || (input && !connected_in && !connected_out)) { + if (pull =3D=3D NRF51_GPIO_PULLDOWN) { + s->in =3D deposit32(s->in, i, 1, 0); + } else if (pull =3D=3D NRF51_GPIO_PULLUP) { + s->in =3D deposit32(s->in, i, 1, 1); + } + } + + /* Self stimulation through internal output driver */ + if (connected_out && !connected_in && input) { + s->in =3D deposit32(s->in, i, 1, out); + } + } + +} + +/* + * Direction is exposed in both the DIR register and the DIR bit + * of each PINs CNF configuration register. Reflect bits for pins in DIR + * to individual pin configuration registers. + */ +static void reflect_dir_bit_in_cnf(NRF51GPIOState *s) +{ + uint32_t value =3D s->dir; + for (size_t i =3D 0; i < NRF51_GPIO_PINS; i++) { + s->cnf[i] =3D (s->cnf[i] & ~(1UL)) | ((value >> i) & 0x01); + } +} + +static uint64_t nrf51_gpio_read(void *opaque, hwaddr offset, unsigned int = size) +{ + NRF51GPIOState *s =3D NRF51_GPIO(opaque); + uint64_t r =3D 0; + size_t idx; + + switch (offset) { + case NRF51_GPIO_REG_OUT ... NRF51_GPIO_REG_OUTCLR: + r =3D s->out; + break; + + case NRF51_GPIO_REG_IN: + r =3D s->in; + break; + + case NRF51_GPIO_REG_DIR ... NRF51_GPIO_REG_DIRCLR: + r =3D s->dir; + break; + + case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: + idx =3D (offset - NRF51_GPIO_REG_CNF_START) / 4; + r =3D s->cnf[idx]; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + trace_nrf51_gpio_read(offset, r); + + return r; +} + +static void nrf51_gpio_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51GPIOState *s =3D NRF51_GPIO(opaque); + size_t idx; + + trace_nrf51_gpio_write(offset, value); + + switch (offset) { + case NRF51_GPIO_REG_OUT: + s->out =3D value; + break; + + case NRF51_GPIO_REG_OUTSET: + s->out |=3D value; + break; + + case NRF51_GPIO_REG_OUTCLR: + s->out &=3D ~value; + break; + + case NRF51_GPIO_REG_DIR: + s->dir =3D value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_DIRSET: + s->dir |=3D value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_DIRCLR: + s->dir &=3D ~value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: + idx =3D (offset - NRF51_GPIO_REG_CNF_START) / 4; + s->cnf[idx] =3D value; + /* direction is exposed in both the DIR register and the DIR bit + * of each PINs CNF configuration register. */ + s->dir =3D (s->dir & ~(1UL << idx)) | ((value & 0x01) << idx); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_state(s); +} + +static const MemoryRegionOps gpio_ops =3D { + .read =3D nrf51_gpio_read, + .write =3D nrf51_gpio_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +static void nrf51_gpio_set(void *opaque, int line, int value) +{ + NRF51GPIOState *s =3D NRF51_GPIO(opaque); + + trace_nrf51_gpio_set(line, value); + + assert(line >=3D 0 && line < NRF51_GPIO_PINS); + + s->in_mask =3D deposit32(s->in_mask, line, 1, value >=3D 0); + if (value >=3D 0) { + s->in =3D deposit32(s->in, line, 1, value !=3D 0); + } + + update_state(s); +} + +static void nrf51_gpio_reset(DeviceState *dev) +{ + NRF51GPIOState *s =3D NRF51_GPIO(dev); + size_t i; + + s->out =3D 0; + s->old_out =3D 0; + s->old_out_connected =3D 0; + s->in =3D 0; + s->in_mask =3D 0; + s->dir =3D 0; + + for (i =3D 0; i < NRF51_GPIO_PINS; i++) { + s->cnf[i] =3D 0x00000002; + } +} + +static const VMStateDescription vmstate_nrf51_gpio =3D { + .name =3D TYPE_NRF51_GPIO, + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(out, NRF51GPIOState), + VMSTATE_UINT32(in, NRF51GPIOState), + VMSTATE_UINT32(in_mask, NRF51GPIOState), + VMSTATE_UINT32(dir, NRF51GPIOState), + VMSTATE_UINT32_ARRAY(cnf, NRF51GPIOState, NRF51_GPIO_PINS), + VMSTATE_UINT32(old_out, NRF51GPIOState), + VMSTATE_UINT32(old_out_connected, NRF51GPIOState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_gpio_init(Object *obj) +{ + NRF51GPIOState *s =3D NRF51_GPIO(obj); + + memory_region_init_io(&s->mmio, obj, &gpio_ops, s, + TYPE_NRF51_GPIO, NRF51_GPIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(s), nrf51_gpio_set, NRF51_GPIO_PINS); + qdev_init_gpio_out(DEVICE(s), s->output, NRF51_GPIO_PINS); +} + +static void nrf51_gpio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_nrf51_gpio; + dc->reset =3D nrf51_gpio_reset; + dc->desc =3D "nRF51 GPIO"; +} + +static const TypeInfo nrf51_gpio_info =3D { + .name =3D TYPE_NRF51_GPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51GPIOState), + .instance_init =3D nrf51_gpio_init, + .class_init =3D nrf51_gpio_class_init +}; + +static void nrf51_gpio_register_types(void) +{ + type_register_static(&nrf51_gpio_info); +} + +type_init(nrf51_gpio_register_types) diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events new file mode 100644 index 0000000000..cb41a89756 --- /dev/null +++ b/hw/gpio/trace-events @@ -0,0 +1,7 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/gpio/nrf51_gpio.c +nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0= x%" PRIx64 +nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " va= lue 0x%" PRIx64 +nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRI= i64 +nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 = " value %" PRIi64 \ No newline at end of file diff --git a/include/hw/gpio/nrf51_gpio.h b/include/hw/gpio/nrf51_gpio.h new file mode 100644 index 0000000000..337ee534bb --- /dev/null +++ b/include/hw/gpio/nrf51_gpio.h @@ -0,0 +1,69 @@ +/* + * nRF51 System-on-Chip general purpose input/output register definition + * + * QEMU interface: + * + sysbus MMIO regions 0: GPIO registers + * + Unnamed GPIO inputs 0-31: Set tri-state input level for GPIO pin. + * Level -1: Externally Disconnected/Floating; Pull-up/down will be rega= rded + * Level 0: Input externally driven LOW + * Level 1: Input externally driven HIGH + * + Unnamed GPIO outputs 0-31: + * Level -1: Disconnected/Floating + * Level 0: Driven LOW + * Level 1: Driven HIGH + * + * Accuracy of the peripheral model: + * + The nRF51 GPIO output driver supports two modes, standard and high-cu= rrent + * mode. These different drive modes are not modeled and handled the sam= e. + * + Pin SENSEing is not modeled/implemented. + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + */ +#ifndef NRF51_GPIO_H +#define NRF51_GPIO_H + +#include "hw/sysbus.h" +#define TYPE_NRF51_GPIO "nrf51_soc.gpio" +#define NRF51_GPIO(obj) OBJECT_CHECK(NRF51GPIOState, (obj), TYPE_NRF51_GPI= O) + +#define NRF51_GPIO_PINS 32 + +#define NRF51_GPIO_SIZE 0x1000 + +#define NRF51_GPIO_REG_OUT 0x504 +#define NRF51_GPIO_REG_OUTSET 0x508 +#define NRF51_GPIO_REG_OUTCLR 0x50C +#define NRF51_GPIO_REG_IN 0x510 +#define NRF51_GPIO_REG_DIR 0x514 +#define NRF51_GPIO_REG_DIRSET 0x518 +#define NRF51_GPIO_REG_DIRCLR 0x51C +#define NRF51_GPIO_REG_CNF_START 0x700 +#define NRF51_GPIO_REG_CNF_END 0x77F + +#define NRF51_GPIO_PULLDOWN 1 +#define NRF51_GPIO_PULLUP 3 + +typedef struct NRF51GPIOState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq irq; + + uint32_t out; + uint32_t in; + uint32_t in_mask; + uint32_t dir; + uint32_t cnf[NRF51_GPIO_PINS]; + + uint32_t old_out; + uint32_t old_out_connected; + + qemu_irq output[NRF51_GPIO_PINS]; +} NRF51GPIOState; + + +#endif --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540945721302710.2603509590834; Tue, 30 Oct 2018 17:28:41 -0700 (PDT) Received: from localhost ([::1]:56213 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeNE-0007gU-3x for importer@patchew.org; Tue, 30 Oct 2018 20:28:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41636) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKo-0004v4-Ep for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKn-0000Go-8B for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:10 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60470) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKl-0000FF-1m; Tue, 30 Oct 2018 20:26:07 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id 2EC244FB71; Wed, 31 Oct 2018 01:23:32 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:23 -0400 Message-Id: <20181031002526.14262-10-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 09/13] arm: Instantiate NRF51 general purpose I/O X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , "open list:NRF51" , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Instantiates GPIO peripheral model Signed-off-by: Steffen G=C3=B6rtz --- hw/arm/nrf51_soc.c | 16 ++++++++++++++++ include/hw/arm/nrf51_soc.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index fd0efd0ee8..695b335dc5 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -128,6 +128,19 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Er= ror **errp) mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr= , 0); =20 + /* GPIO */ + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr= , 0); + + /* Pass all GPIOs to the SOC layer so they are available to the board = */ + qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); + =20 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); @@ -157,6 +170,9 @@ static void nrf51_soc_init(Object *obj) =20 sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_= NVM); =20 + sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), + TYPE_NRF51_GPIO); + } =20 static Property nrf51_soc_properties[] =3D { diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index c3f4d5bcdc..d4a48ccf91 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -15,6 +15,7 @@ #include "hw/char/nrf51_uart.h" #include "hw/misc/nrf51_rng.h" #include "hw/nvram/nrf51_nvm.h" +#include "hw/gpio/nrf51_gpio.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ @@ -30,6 +31,7 @@ typedef struct NRF51State { NRF51UARTState uart; NRF51RNGState rng; NRF51NVMState nvm; + NRF51GPIOState gpio; =20 MemoryRegion iomem; MemoryRegion sram; --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540946299380401.4943508370865; Tue, 30 Oct 2018 17:38:19 -0700 (PDT) Received: from localhost ([::1]:56272 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeWY-0008Km-2p for importer@patchew.org; Tue, 30 Oct 2018 20:38:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41638) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKo-0004v5-GR for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKn-0000Gj-4R for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:10 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60472) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKm-0000GJ-Qb for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:09 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id A8A944FB76; Wed, 31 Oct 2018 01:23:33 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:24 -0400 Message-Id: <20181031002526.14262-11-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 10/13] tests/microbit-test: Add Tests for nRF51 GPIO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Thomas Huth , Joel Stanley , Paolo Bonzini , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The test suite for the nRF51 GPIO peripheral for now only tests initial state. Additionally a set of tests testing an implementation detail of the model are included. Signed-off-by: Steffen G=C3=B6rtz --- tests/microbit-test.c | 122 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/tests/microbit-test.c b/tests/microbit-test.c index 981a36ed82..0ed64e1962 100644 --- a/tests/microbit-test.c +++ b/tests/microbit-test.c @@ -20,6 +20,7 @@ =20 #include "hw/arm/nrf51.h" #include "hw/nvram/nrf51_nvm.h" +#include "hw/gpio/nrf51_gpio.h" =20 #define FLASH_SIZE (256 * NRF51_PAGE_SIZE) =20 @@ -100,6 +101,126 @@ static void test_nrf51_nvmc(void) } } =20 +static void test_nrf51_gpio(void) +{ + size_t i; + uint32_t actual, expected; + + struct { + hwaddr addr; + uint32_t expected; + } reset_state[] =3D { + {NRF51_GPIO_REG_OUT, 0x00000000}, {NRF51_GPIO_REG_OUTSET, 0x000000= 00}, + {NRF51_GPIO_REG_OUTCLR, 0x00000000}, {NRF51_GPIO_REG_IN, 0x0000000= 0}, + {NRF51_GPIO_REG_DIR, 0x00000000}, {NRF51_GPIO_REG_DIRSET, 0x000000= 00}, + {NRF51_GPIO_REG_DIRCLR, 0x00000000} + }; + + /* Check reset state */ + for (i =3D 0; i < ARRAY_SIZE(reset_state); i++) { + expected =3D reset_state[i].expected; + actual =3D readl(NRF51_GPIO_BASE + reset_state[i].addr); + g_assert_cmpuint(actual, =3D=3D, expected); + } + + for (i =3D 0; i < NRF51_GPIO_PINS; i++) { + expected =3D 0x00000002; + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START + i * = 4); + g_assert_cmpuint(actual, =3D=3D, expected); + } + + /* Check dir bit consistency between dir and cnf */ + /* Check set via DIRSET */ + expected =3D 0x80000001; + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRSET, expected); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, =3D=3D, expected); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + + /* Check clear via DIRCLR */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRCLR, 0x80000001); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, =3D=3D, 0x00000000); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + + /* Check set via DIR */ + expected =3D 0x80000001; + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, expected); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, =3D=3D, expected); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + + /* Reset DIR */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, 0x00000000); + + /* Check Input propagates */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x00); + set_irq_in("/machine/nrf51", "unnamed-gpio-in", 0, 0); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + set_irq_in("/machine/nrf51", "unnamed-gpio-in", 0, 1); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + set_irq_in("/machine/nrf51", "unnamed-gpio-in", 0, -1); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + + /* Check pull-up working */ + set_irq_in("/machine/nrf51", "unnamed-gpio-in", 0, 0); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b1110); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + + /* Check pull-down working */ + set_irq_in("/machine/nrf51", "unnamed-gpio-in", 0, 1); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0110); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + set_irq_in("/machine/nrf51", "unnamed-gpio-in", 0, -1); + + /* Check Output propagates */ + irq_intercept_out("/machine/nrf51"); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0011); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + g_assert_true(get_irq(0)); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); + g_assert_false(get_irq(0)); + + /* Check self-stimulation */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x01); + + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); + actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, =3D=3D, 0x00); + + /* Check short-circuit - generates an guest_error which must be checked + manually as long as qtest can not scan qemu_log messages */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + set_irq_in("/machine/nrf51", "unnamed-gpio-in", 0, 0); +} + int main(int argc, char **argv) { int ret; @@ -109,6 +230,7 @@ int main(int argc, char **argv) global_qtest =3D qtest_initf("-machine microbit"); =20 qtest_add_func("/microbit/nrf51/nvmc", test_nrf51_nvmc); + qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); =20 ret =3D g_test_run(); =20 --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540946355426667.7325454113229; Tue, 30 Oct 2018 17:39:15 -0700 (PDT) Received: from localhost ([::1]:56276 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeXO-0000nh-6I for importer@patchew.org; Tue, 30 Oct 2018 20:39:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKq-0004v7-O4 for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeKo-0000Hr-SN for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:12 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60488) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeKo-0000HG-Hw for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:10 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id 69ECC4FB72; Wed, 31 Oct 2018 01:23:35 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:25 -0400 Message-Id: <20181031002526.14262-12-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 11/13] hw/timer/nrf51_timer: Add nRF51 Timer peripheral X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This patch adds the model for the nRF51 timer peripheral. Currently, only the TIMER mode is implemented. Signed-off-by: Steffen G=C3=B6rtz --- hw/timer/Makefile.objs | 1 + hw/timer/nrf51_timer.c | 358 +++++++++++++++++++++++++++++++++ hw/timer/trace-events | 5 + include/hw/timer/nrf51_timer.h | 77 +++++++ 4 files changed, 441 insertions(+) create mode 100644 hw/timer/nrf51_timer.c create mode 100644 include/hw/timer/nrf51_timer.h diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index b32194d153..0e9a4530f8 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -23,6 +23,7 @@ common-obj-$(CONFIG_IMX) +=3D imx_gpt.o common-obj-$(CONFIG_LM32) +=3D lm32_timer.o common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-sysctl.o common-obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx-zynqmp-rtc.o +common-obj-$(CONFIG_NRF51_SOC) +=3D nrf51_timer.o =20 obj-$(CONFIG_ALTERA_TIMER) +=3D altera_timer.o obj-$(CONFIG_EXYNOS4) +=3D exynos4210_mct.o diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c new file mode 100644 index 0000000000..b0a2850cb5 --- /dev/null +++ b/hw/timer/nrf51_timer.c @@ -0,0 +1,358 @@ +/* + * nRF51 System-on-Chip Timer peripheral + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/arm/nrf51.h" +#include "hw/timer/nrf51_timer.h" +#include "trace.h" + +#define TIMER_CLK 16000000ULL + +static uint8_t const bitwidths[] =3D {16, 8, 24, 32}; +#define BWM(x) ((1UL << bitwidths[x]) - 1) + +typedef enum { + NRF51_TIMER_TIMER =3D 0, + NRF51_TIMER_COUNTER =3D 1 +} Nrf51TimerMode; + + +static inline uint64_t ns_to_ticks(NRF51TimerState *s, uint64_t ns) +{ + uint64_t t =3D NANOSECONDS_PER_SECOND * (1 << s->prescaler); + return muldiv64(ns, TIMER_CLK, t); +} + +static inline uint64_t ticks_to_ns(NRF51TimerState *s, uint64_t ticks) +{ + ticks *=3D (1 << s->prescaler); + return muldiv64(ticks, NANOSECONDS_PER_SECOND, TIMER_CLK); +} + +static void update_irq(NRF51TimerState *s) +{ + bool flag =3D false; + size_t i; + + for (i =3D 0; i < NRF51_TIMER_REG_COUNT; i++) { + flag |=3D s->events_compare[i] && extract32(s->inten, 16 + i, 1); + } + qemu_set_irq(s->irq, flag); +} + +static void update_events(NRF51TimerState *s, uint64_t now) +{ + uint64_t strobe; + uint64_t tick; + uint64_t cc; + size_t i; + bool occured; + + strobe =3D ns_to_ticks(s, now - s->last_visited); + tick =3D ns_to_ticks(s, s->last_visited - s->time_offset) & BWM(s->bit= mode); + + for (i =3D 0; i < NRF51_TIMER_REG_COUNT; i++) { + cc =3D s->cc[i]; + + if (tick < cc) { + occured =3D (cc - tick) <=3D strobe; + } else { + occured =3D ((cc + (1UL << bitwidths[s->bitmode])) - tick) <= =3D strobe; + } + + s->events_compare[i] |=3D occured; + } + + s->last_visited =3D now; +} + +static int cmpfunc(const void *a, const void *b) +{ + return *(uint32_t *)a - *(uint32_t *)b; +} + +static uint64_t get_next_timeout(NRF51TimerState *s, uint64_t now) +{ + uint64_t r; + size_t idx; + + uint64_t tick =3D (ns_to_ticks(s, now - s->time_offset)) & BWM(s->bitm= ode); + int8_t next =3D -1; + + for (idx =3D 0; idx < NRF51_TIMER_REG_COUNT; idx++) { + if (s->cc_sorted[idx] > tick) { + next =3D idx; + break; + } + } + + if (next =3D=3D -1) { + r =3D s->cc_sorted[0] + (1UL << bitwidths[s->bitmode]); + } else { + r =3D s->cc_sorted[next]; + } + + return now + ticks_to_ns(s, r - tick); +} + +static void update_internal_state(NRF51TimerState *s, uint64_t now) +{ + if (s->running) { + timer_mod(&s->timer, get_next_timeout(s, now)); + } else { + timer_del(&s->timer); + } + + update_irq(s); +} + +static void timer_expire(void *opaque) +{ + NRF51TimerState *s =3D NRF51_TIMER(opaque); + uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + update_events(s, now); + update_internal_state(s, now); +} + +static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int= size) +{ + NRF51TimerState *s =3D NRF51_TIMER(opaque); + uint64_t r =3D 0; + + switch (offset) { + case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3: + r =3D s->events_compare[(offset - NRF51_TIMER_EVENT_COMPARE_0) / 4= ]; + break; + case NRF51_TIMER_REG_SHORTS: + r =3D s->shorts; + break; + case NRF51_TIMER_REG_INTENSET: + r =3D s->inten; + break; + case NRF51_TIMER_REG_INTENCLR: + r =3D s->inten; + break; + case NRF51_TIMER_REG_MODE: + r =3D s->mode; + break; + case NRF51_TIMER_REG_BITMODE: + r =3D s->bitmode; + break; + case NRF51_TIMER_REG_PRESCALER: + r =3D s->prescaler; + break; + case NRF51_TIMER_REG_CC0 ... NRF51_TIMER_REG_CC3: + r =3D s->cc[(offset - NRF51_TIMER_REG_CC0) / 4]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + trace_nrf51_timer_read(offset, r, size); + + return r; +} + +static inline void update_cc_sorted(NRF51TimerState *s) +{ + memcpy(s->cc_sorted, s->cc, sizeof(s->cc_sorted)); + qsort(s->cc_sorted, NRF51_TIMER_REG_COUNT, sizeof(uint32_t), cmpfunc); +} + +static void nrf51_timer_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51TimerState *s =3D NRF51_TIMER(opaque); + uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + size_t idx; + + trace_nrf51_timer_write(offset, value, size); + + switch (offset) { + case NRF51_TIMER_TASK_START: + if (value =3D=3D NRF51_TRIGGER_TASK) { + s->running =3D true; + } + break; + case NRF51_TIMER_TASK_STOP: + case NRF51_TIMER_TASK_SHUTDOWN: + if (value =3D=3D NRF51_TRIGGER_TASK) { + s->running =3D false; + } + break; + case NRF51_TIMER_TASK_COUNT: + if (value =3D=3D NRF51_TRIGGER_TASK) { + qemu_log_mask(LOG_UNIMP, "COUNTER mode not implemented\n"); + } + break; + case NRF51_TIMER_TASK_CLEAR: + if (value =3D=3D NRF51_TRIGGER_TASK) { + s->time_offset =3D now; + s->last_visited =3D now; + } + break; + case NRF51_TIMER_TASK_CAPTURE_0 ... NRF51_TIMER_TASK_CAPTURE_3: + if (value =3D=3D NRF51_TRIGGER_TASK) { + idx =3D (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4; + s->cc[idx] =3D ns_to_ticks(s, now - s->time_offset) & BWM(s->b= itmode); + update_cc_sorted(s); + } + break; + case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3: + if (value =3D=3D NRF51_EVENT_CLEAR) { + s->events_compare[(offset - NRF51_TIMER_EVENT_COMPARE_0) / 4] = =3D 0; + } + break; + case NRF51_TIMER_REG_SHORTS: + s->shorts =3D value & NRF51_TIMER_REG_SHORTS_MASK; + break; + case NRF51_TIMER_REG_INTENSET: + s->inten |=3D value & NRF51_TIMER_REG_INTEN_MASK; + break; + case NRF51_TIMER_REG_INTENCLR: + s->inten &=3D ~(value & NRF51_TIMER_REG_INTEN_MASK); + break; + case NRF51_TIMER_REG_MODE: + if (s->mode !=3D NRF51_TIMER_TIMER) { + qemu_log_mask(LOG_UNIMP, "COUNTER mode not implemented\n"); + return; + } + s->mode =3D value; + break; + case NRF51_TIMER_REG_BITMODE: + if (s->mode =3D=3D NRF51_TIMER_TIMER && s->running) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: erroneous change of BITMODE while timer is running\n", + __func__); + } + s->bitmode =3D value & NRF51_TIMER_REG_BITMODE_MASK; + s->time_offset =3D now; + s->last_visited =3D now; + break; + case NRF51_TIMER_REG_PRESCALER: + if (s->mode =3D=3D NRF51_TIMER_TIMER && s->running) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: erroneous change of PRESCALER while timer is running\= n", + __func__); + } + s->prescaler =3D value & NRF51_TIMER_REG_PRESCALER_MASK; + s->time_offset =3D now; + s->last_visited =3D now; + break; + case NRF51_TIMER_REG_CC0 ... NRF51_TIMER_REG_CC3: + s->cc[(offset - NRF51_TIMER_REG_CC0) / 4] =3D value & BWM(s->bitmo= de); + update_cc_sorted(s); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_internal_state(s, now); +} + +static const MemoryRegionOps rng_ops =3D { + .read =3D nrf51_timer_read, + .write =3D nrf51_timer_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +static void nrf51_timer_init(Object *obj) +{ + NRF51TimerState *s =3D NRF51_TIMER(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &rng_ops, s, + TYPE_NRF51_TIMER, NRF51_TIMER_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + + timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL, timer_expire, s); +} + +static void nrf51_timer_reset(DeviceState *dev) +{ + NRF51TimerState *s =3D NRF51_TIMER(dev); + + s->running =3D false; + + memset(s->events_compare, 0x00, sizeof(s->events_compare)); + memset(s->cc, 0x00, sizeof(s->cc)); + memset(s->cc_sorted, 0x00, sizeof(s->cc_sorted)); + s->shorts =3D 0x00; + s->inten =3D 0x00; + s->mode =3D 0x00; + s->bitmode =3D 0x00; + s->prescaler =3D 0x00; + + uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + s->time_offset =3D now; + s->last_visited =3D now; + + update_internal_state(s, now); +} + +static const VMStateDescription vmstate_nrf51_timer =3D { + .name =3D TYPE_NRF51_TIMER, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_TIMER(timer, NRF51TimerState), + VMSTATE_BOOL(running, NRF51TimerState), + VMSTATE_UINT64(time_offset, NRF51TimerState), + VMSTATE_UINT64(last_visited, NRF51TimerState), + VMSTATE_UINT8_ARRAY(events_compare, NRF51TimerState, + NRF51_TIMER_REG_COUNT), + VMSTATE_UINT32_ARRAY(cc, NRF51TimerState, NRF51_TIMER_REG_COUNT), + VMSTATE_UINT32_ARRAY(cc_sorted, NRF51TimerState, NRF51_TIMER_REG_C= OUNT), + VMSTATE_UINT32(shorts, NRF51TimerState), + VMSTATE_UINT32(inten, NRF51TimerState), + VMSTATE_UINT32(mode, NRF51TimerState), + VMSTATE_UINT32(bitmode, NRF51TimerState), + VMSTATE_UINT32(prescaler, NRF51TimerState), + VMSTATE_END_OF_LIST() + } +}; + +static Property nrf51_timer_properties[] =3D { + DEFINE_PROP_END_OF_LIST(), +}; + +static void nrf51_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D nrf51_timer_properties; + dc->reset =3D nrf51_timer_reset; + dc->vmsd =3D &vmstate_nrf51_timer; +} + +static const TypeInfo nrf51_timer_info =3D { + .name =3D TYPE_NRF51_TIMER, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51TimerState), + .instance_init =3D nrf51_timer_init, + .class_init =3D nrf51_timer_class_init +}; + +static void nrf51_timer_register_types(void) +{ + type_register_static(&nrf51_timer_info); +} + +type_init(nrf51_timer_register_types) diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 75bd3b1042..0144a68951 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -72,3 +72,8 @@ sun4v_rtc_write(uint64_t addr, uint64_t value) "write: ad= dr 0x%" PRIx64 " value =20 # hw/timer/xlnx-zynqmp-rtc.c xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, i= nt sec) "Get time from host: %d-%d-%d %2d:%02d:%02d" + +# hw/timer/nrf51_timer.c +nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr = 0x%" PRIx64 " data 0x%" PRIx32 " size %u" +nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write add= r 0x%" PRIx64 " data 0x%" PRIx32 " size %u" + diff --git a/include/hw/timer/nrf51_timer.h b/include/hw/timer/nrf51_timer.h new file mode 100644 index 0000000000..a607491c94 --- /dev/null +++ b/include/hw/timer/nrf51_timer.h @@ -0,0 +1,77 @@ +/* + * nRF51 System-on-Chip Timer peripheral + * + * QEMU interface: + * + sysbus MMIO regions 0: GPIO registers + * + sysbus irq + * + * Accuracy of the peripheral model: + * + Only TIMER mode is implemented, COUNTER mode is not implemented. + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ +#ifndef NRF51_TIMER_H +#define NRF51_TIMER_H + +#include "hw/sysbus.h" +#include "qemu/timer.h" +#define TYPE_NRF51_TIMER "nrf51_soc.timer" +#define NRF51_TIMER(obj) OBJECT_CHECK(NRF51TimerState, (obj), TYPE_NRF51_T= IMER) + +#define NRF51_TIMER_REG_COUNT 4 + +#define NRF51_TIMER_SIZE 0x1000 + +#define NRF51_TIMER_TASK_START 0x000 +#define NRF51_TIMER_TASK_STOP 0x004 +#define NRF51_TIMER_TASK_COUNT 0x008 +#define NRF51_TIMER_TASK_CLEAR 0x00C +#define NRF51_TIMER_TASK_SHUTDOWN 0x010 +#define NRF51_TIMER_TASK_CAPTURE_0 0x040 +#define NRF51_TIMER_TASK_CAPTURE_3 0x04C + +#define NRF51_TIMER_EVENT_COMPARE_0 0x140 +#define NRF51_TIMER_EVENT_COMPARE_3 0x14C + +#define NRF51_TIMER_REG_SHORTS 0x200 +#define NRF51_TIMER_REG_SHORTS_MASK 0xf0f +#define NRF51_TIMER_REG_INTENSET 0x304 +#define NRF51_TIMER_REG_INTENCLR 0x308 +#define NRF51_TIMER_REG_INTEN_MASK 0xf0000 +#define NRF51_TIMER_REG_MODE 0x504 +#define NRF51_TIMER_REG_MODE_MASK 0x01 +#define NRF51_TIMER_REG_BITMODE 0x508 +#define NRF51_TIMER_REG_BITMODE_MASK 0x03 +#define NRF51_TIMER_REG_PRESCALER 0x510 +#define NRF51_TIMER_REG_PRESCALER_MASK 0x0F +#define NRF51_TIMER_REG_CC0 0x540 +#define NRF51_TIMER_REG_CC3 0x54C + +typedef struct NRF51TimerState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + + QEMUTimer timer; + + bool running; + + uint64_t time_offset; + uint64_t last_visited; + + uint8_t events_compare[NRF51_TIMER_REG_COUNT]; + uint32_t cc[NRF51_TIMER_REG_COUNT]; + uint32_t cc_sorted[NRF51_TIMER_REG_COUNT]; + uint32_t shorts; + uint32_t inten; + uint32_t mode; + uint32_t bitmode; + uint32_t prescaler; +} NRF51TimerState; + + +#endif --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540946551077804.2984386016741; Tue, 30 Oct 2018 17:42:31 -0700 (PDT) Received: from localhost ([::1]:56306 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeaY-0003dp-Rk for importer@patchew.org; Tue, 30 Oct 2018 20:42:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeLZ-0005T5-FN for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeLY-0000dX-LW for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:26:57 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60506) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeLU-0000IE-1t; Tue, 30 Oct 2018 20:26:52 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id C89A44FB77; Wed, 31 Oct 2018 01:23:36 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:26 -0400 Message-Id: <20181031002526.14262-13-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 12/13] arm: Instantiate NRF51 Timers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , "open list:NRF51" , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Instantiates TIMER0 - TIMER2 Signed-off-by: Steffen G=C3=B6rtz --- hw/arm/nrf51_soc.c | 27 +++++++++++++++++++++++++++ include/hw/arm/nrf51_soc.h | 4 ++++ 2 files changed, 31 insertions(+) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 695b335dc5..c29b80c0ca 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -40,6 +40,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error= **errp) NRF51State *s =3D NRF51_SOC(dev_soc); MemoryRegion *mr; Error *err =3D NULL; + uint8_t i =3D 0; + hwaddr base_addr =3D 0; =20 if (!s->board_memory) { error_setg(errp, "memory property was not set"); @@ -141,6 +143,22 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Er= ror **errp) /* Pass all GPIOs to the SOC layer so they are available to the board = */ qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); =20 + /* TIMER */ + for (i =3D 0; i < NRF51_NUM_TIMERS; i++) { + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &= err); + if (err) { + error_propagate(errp, err); + return; + } + + base_addr =3D NRF51_TIMER_BASE + i * 0x1000; + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(base_addr))); + } + =20 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); @@ -150,6 +168,8 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Err= or **errp) =20 static void nrf51_soc_init(Object *obj) { + uint8_t i =3D 0; + NRF51State *s =3D NRF51_SOC(obj); =20 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); @@ -173,6 +193,13 @@ static void nrf51_soc_init(Object *obj) sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), TYPE_NRF51_GPIO); =20 + for (i =3D 0; i < NRF51_NUM_TIMERS; i++) { + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], + sizeof(s->timer[i]), TYPE_NRF51_TIMER); + + } + + } =20 static Property nrf51_soc_properties[] =3D { diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index d4a48ccf91..89525dcb39 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -16,11 +16,14 @@ #include "hw/misc/nrf51_rng.h" #include "hw/nvram/nrf51_nvm.h" #include "hw/gpio/nrf51_gpio.h" +#include "hw/timer/nrf51_timer.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC) =20 +#define NRF51_NUM_TIMERS 3 + typedef struct NRF51State { /*< private >*/ SysBusDevice parent_obj; @@ -32,6 +35,7 @@ typedef struct NRF51State { NRF51RNGState rng; NRF51NVMState nvm; NRF51GPIOState gpio; + NRF51TimerState timer[NRF51_NUM_TIMERS]; =20 MemoryRegion iomem; MemoryRegion sram; --=20 2.19.1 From nobody Tue May 7 00:48:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540945912103248.81075921882382; Tue, 30 Oct 2018 17:31:52 -0700 (PDT) Received: from localhost ([::1]:56231 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeQE-0001bp-Cq for importer@patchew.org; Tue, 30 Oct 2018 20:31:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeLc-0005Vu-CE for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:27:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gHeLb-0000f8-Ja for qemu-devel@nongnu.org; Tue, 30 Oct 2018 20:27:00 -0400 Received: from steffen-goertz.de ([88.198.119.201]:60510) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHeLZ-0000Iw-Ps; Tue, 30 Oct 2018 20:26:57 -0400 Received: from gouranga.fios-router.home (pool-71-183-97-129.nycmny.fios.verizon.net [71.183.97.129]) by steffen-goertz.de (Postfix) with ESMTPSA id 52CB84FB76; Wed, 31 Oct 2018 01:23:38 +0100 (CET) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2018 20:25:27 -0400 Message-Id: <20181031002526.14262-14-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181031002526.14262-1-contrib@steffen-goertz.de> References: <20181031002526.14262-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH v3 13/13] arm: Add Clock peripheral stub to NRF51 SOC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , "open list:NRF51" , Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This stubs enables the microbit-micropython firmware to run on the microbit machine. Signed-off-by: Steffen G=C3=B6rtz --- hw/arm/nrf51_soc.c | 27 +++++++++++++++++++++++++++ include/hw/arm/nrf51_soc.h | 1 + 2 files changed, 28 insertions(+) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index c29b80c0ca..bccf2b9b2c 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -35,6 +35,26 @@ =20 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) =20 +static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", + __func__, addr, size); + return 1; +} + +static void clock_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]= \n", + __func__, addr, data, size); +} + +static const MemoryRegionOps clock_ops =3D { + .read =3D clock_read, + .write =3D clock_write +}; + + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s =3D NRF51_SOC(dev_soc); @@ -159,6 +179,13 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Er= ror **errp) BASE_TO_IRQ(base_addr))); } =20 + /* STUB Peripherals */ + memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, + "nrf51_soc.clock", 0x1000); + memory_region_add_subregion_overlap(&s->container, + NRF51_IOMEM_BASE, &s->clock, -1); + + =20 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 89525dcb39..4610d0c7ae 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -40,6 +40,7 @@ typedef struct NRF51State { MemoryRegion iomem; MemoryRegion sram; MemoryRegion flash; + MemoryRegion clock; =20 uint32_t sram_size; uint32_t flash_size; --=20 2.19.1