From nobody Thu Nov 6 12:12:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540829849995179.23470612860274; Mon, 29 Oct 2018 09:17:29 -0700 (PDT) Received: from localhost ([::1]:46588 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHAEG-0004lM-AD for importer@patchew.org; Mon, 29 Oct 2018 12:17:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47172) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9rk-0000gH-TO for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9rb-0000gK-Ga for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:05 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:34100) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gH9rV-0000Yg-QH for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:55 -0400 Received: by mail-wr1-x444.google.com with SMTP id l6-v6so9278733wrt.1 for ; Mon, 29 Oct 2018 08:53:51 -0700 (PDT) Received: from cloudburst.twiddle.net ([5.148.65.242]) by smtp.gmail.com with ESMTPSA id p3-v6sm4700517wre.47.2018.10.29.08.53.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Oct 2018 08:53:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LZQNZ6rcVxWOWRYJTTswlGPMH894sJFeWGghPgY04yI=; b=hqhWDH5bd9BtnniyXouzhL/u9ulvDM23+tT3KBJelBICF3HTKQIl+fZvjEqT+MhNeN jSHwNkw95O1PMakzAETobdzPQGLb5bPwR5CjdLQ8noAcsM1/gwUDq13zCABEi2vNkx69 hS0iL0lDwgBMlEfBHyX4VeKWjjl4uwILRERBM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LZQNZ6rcVxWOWRYJTTswlGPMH894sJFeWGghPgY04yI=; b=r8638DRvlqbibedO96j2mr0xTKXmhqTtNkTENeYBo1RbKOTq6FHTzCz0gWtngmCYkl KKfN7Rww3e07q2Z6V8wwxZajsq5SYNyhpuXk+yKTASRbOvSt17FAfvvsi/6y91dorTmm 9ucXATp0gTzg9EwAWh8FfXVzLBaCUqiroLYJRYPfvl+m3fpOFWTmpnnrY04Z7nMDttgF fSjwZsEsIQD5bGhiPpgkJttbs0BAfmemsPX7CHteH0czosW4byFe/stJXvr/BeCPtdjB u9Z1syKVfzDXeZ07DtQgfCo1Jxo2XOqSrxoyZ9WR6jAI+F2dvyFrcXo2C9rjrsD1TGhz fxEg== X-Gm-Message-State: AGRZ1gKRD01zOwRMEzz/mokKX21n0DDhBjmI4n7Xh7f8hhFjxpmvmbGa 12A3dDZXkn1X51Ol1CycaGq/Ia5vSQM= X-Google-Smtp-Source: AJdET5cpT1K7uc9hw1/YYEVHzGq+afJmaNdT/XlzJ9AMGfkQGQ+lMfFsH5s41O0AH1s5Eu4O/IXgdQ== X-Received: by 2002:adf:bf10:: with SMTP id p16-v6mr14431007wrh.235.1540828429538; Mon, 29 Oct 2018 08:53:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 15:53:39 +0000 Message-Id: <20181029155339.15280-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181029155339.15280-1-richard.henderson@linaro.org> References: <20181029155339.15280-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 4/4] target/arm: Install ASIDs for EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The VMID is the ASID for the 2nd stage page lookup. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f767467dcf..4b14f2c05b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2805,17 +2805,23 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D CPU(arm_env_get_cpu(env)); + int vmid; =20 - /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ - if (raw_read(env, ri) !=3D value) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - raw_write(env, ri, value); - } + raw_write(env, ri, value); + + /* + * TODO: with ARMv8.1-VMID16, aarch64 must examine VTCR.VS + * (re-evaluating with changes to VTCR) then use bits [63:48]. + */ + vmid =3D extract64(value, 48, 8); + + /* + * A change in VMID to the stage2 page table (S2NS) invalidates + * the combined stage 1&2 tlbs (S12NSE1 and S12NSE0). + */ + tlb_set_asid_for_mmuidx(cs, vmid, ARMMMUIdxBit_S2NS, + ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0); } =20 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { --=20 2.17.2