From nobody Thu Nov 6 12:12:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540830764375471.4535150951681; Mon, 29 Oct 2018 09:32:44 -0700 (PDT) Received: from localhost ([::1]:46739 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHASz-0005z2-SG for importer@patchew.org; Mon, 29 Oct 2018 12:32:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47173) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9rk-0000gI-TM for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9re-0000in-Gv for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:05 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:33163) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gH9rX-0000Xh-Cx for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:57 -0400 Received: by mail-wr1-x443.google.com with SMTP id u1-v6so9295862wrn.0 for ; Mon, 29 Oct 2018 08:53:50 -0700 (PDT) Received: from cloudburst.twiddle.net ([5.148.65.242]) by smtp.gmail.com with ESMTPSA id p3-v6sm4700517wre.47.2018.10.29.08.53.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Oct 2018 08:53:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ufjQzo+SI6PyAb64orKIBD88Q1YJp7NUSWPWGJqPOn4=; b=Oo+yuyFvZwr7PLQVKIFhdYqNIUdgiB1UnEkCk2Cxjp7fKepzW4i/2RLYyOy+vWYmIS Z/pPgeNPPVdEg2K8d56y6aqRlVzh27xRq5Co/epQeq+lCMHX/BTwUiJlIcNz3+XMxGdR 3sevnYGfDe6Bwhf+7YbFGNIykiv4wSmUBKLLI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ufjQzo+SI6PyAb64orKIBD88Q1YJp7NUSWPWGJqPOn4=; b=Cu2Z9hdssmQ7kMF5J4NgLh7xjuqG+7wD0AXf+RhqdaY9AxnoANiA6FdtPqX+OPgYeA R5aJm3S1rCOMLYKpZdggPXnR+Ze9moI1aORdbSX1TDU9BM4rMSPbXPeAw7Evv/+mkKF4 VACO4gp7QhcMPYrzp2vbcZt+65gd5OJKWlA6ucw+zqkC8JnNpvch6isgWGr9uEOaWerJ 4RS6yuP9cTiB6Vg2J40ioDk+hd3Bpyp9WGYoILqZnhvCTA1I5Lq8JRSfiBdtsDevnUlD F18d7cVWM2P5FFwy9I4+FxpCBIhm+VHRVCr8XwD/5wXZeY8Q65ao0ToqoPqje9JymSdX o2Ww== X-Gm-Message-State: AGRZ1gITt1Xsr1tdLkKc8ScCuT2YlMInbxDMxbANUwyrj89uKDa5EHG+ KV2j/RWyoiGCvXIZqPtLiFupt2csUcQ= X-Google-Smtp-Source: AJdET5f0P3FJUMbxICTLdHbCeMvTuM8NbuyslzRrMGtrQqzUoZTsns2BQZ0LqSeKESU7ne+6Jbt1pg== X-Received: by 2002:adf:ca03:: with SMTP id o3-v6mr4998017wrh.148.1540828428616; Mon, 29 Oct 2018 08:53:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 15:53:38 +0000 Message-Id: <20181029155339.15280-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181029155339.15280-1-richard.henderson@linaro.org> References: <20181029155339.15280-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 3/4] target/arm: Install ASIDs for short-form from EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is less complex than the LPAE case, but still we now avoid the flush in case it is only the PROCID field that is changing. Signed-off-by: Richard Henderson --- target/arm/helper.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 26d6f28793..f767467dcf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -541,17 +541,31 @@ static void fcse_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - - if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) - && !extended_addresses_enabled(env)) { - /* For VMSA (when not using the LPAE long descriptor page table - * format) this register includes the ASID, so do a TLB flush. - * For PMSA it is purely a process ID and no action is needed. - */ - tlb_flush(CPU(cpu)); - } raw_write(env, ri, value); + + /* + * For VMSA (when not using the LPAE long descriptor page table format) + * this register includes the ASID. For PMSA it is purely a process ID + * and no action is needed. + */ + if (!arm_feature(env, ARM_FEATURE_PMSA) && + !extended_addresses_enabled(env)) { + CPUState *cs =3D CPU(arm_env_get_cpu(env)); + int asid =3D extract32(value, 0, 8); + int idxmask; + + switch (ri->secure) { + case ARM_CP_SECSTATE_S: + idxmask =3D ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + break; + case ARM_CP_SECSTATE_NS: + idxmask =3D ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + break; + default: + g_assert_not_reached(); + } + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); + } } =20 /* IS variants of TLB operations must affect all cores */ --=20 2.17.2