From nobody Thu Nov 6 12:12:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15408296956354.820355561770953; Mon, 29 Oct 2018 09:14:55 -0700 (PDT) Received: from localhost ([::1]:46560 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHABq-0001sp-A3 for importer@patchew.org; Mon, 29 Oct 2018 12:14:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9rg-0000cg-BW for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9rX-0000cy-E1 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:58 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41937) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gH9rT-0000WP-Tr for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:52 -0400 Received: by mail-wr1-x42f.google.com with SMTP id x12-v6so9251049wrw.8 for ; Mon, 29 Oct 2018 08:53:48 -0700 (PDT) Received: from cloudburst.twiddle.net ([5.148.65.242]) by smtp.gmail.com with ESMTPSA id p3-v6sm4700517wre.47.2018.10.29.08.53.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Oct 2018 08:53:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AmAE+SggdeN2sPEPO0MNGARzD23BTp2OLLKQlCsNsjA=; b=Yr43/tx4JjmieotNR6WJZlTQ3skSzIidj5lLSDVTmU7ALXPkicDDstdC7aap9z4sjl 1+Y7VQBok+EWvbVc08S1V+Eaq9qT8eW1IiGZo1VXBEZuacdkw0S0yNSEtdRfzZanr7nd rFKbqlcfYb6E9Tdfhly4571s8pV+f/GlTXVjU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AmAE+SggdeN2sPEPO0MNGARzD23BTp2OLLKQlCsNsjA=; b=FA1RX9r3Zch/6OuWzmFxJ+j/Y4lBficfOrKU6mHVSL6CqHouExDw48oHXlF8aptYDe ar0VmokRG3mXgyUeUbKNk0c7qQNXuhWmiZKjiG9tdyDDUQsb08GKtpLUh1Scua/NbJtn kkUDbGeswq5jRuzoRhTsTKp6rmS2ALbSzNp1hVwXrRPkzCDlEVg5LXWUK5W1MXk91Nkq sNiMiaNCn26JLqUaRTNmmWr2X4LMn2yKNJxDJf1yNgE58McOOW6e6lkjeq4worJnLb7H CSTNYmlk3c7gIXARA5qXZ3hE40n4CJr4I3MRssDlljRbeyi5/vXSLD/DoPRsiROX0dIQ L2kQ== X-Gm-Message-State: AGRZ1gIfeVuaocmn+NJiI1xYhkQ1f7uH49xGs0tYKznHZFVTi/qV1UuC aRJJ+9OVgD/epQ8htACY4aX/pvFuxsM= X-Google-Smtp-Source: AJdET5cfGd11wyC1NPisyuuHx/mhWcCUC4sutpow4Kfaob/VVirbAUAlYXSZJZ5XGpQdMeVuz9vANA== X-Received: by 2002:adf:f712:: with SMTP id r18-v6mr14948203wrp.85.1540828426978; Mon, 29 Oct 2018 08:53:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 15:53:37 +0000 Message-Id: <20181029155339.15280-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181029155339.15280-1-richard.henderson@linaro.org> References: <20181029155339.15280-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PATCH 2/4] target/arm: Install ASIDs for long-form from EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In addition to providing the core with the current ASID, this minimizes both the number of flushes due to non-changing ASID as well as the set of mmu_idx that are affected by each flush. In particular, updates to the secure mode registers flushes only the relevant secure mode mmu_idx's, and similarly non-secure updates only affect non-secure mmu_idx's. Signed-off-by: Richard Henderson --- target/arm/helper.c | 73 +++++++++++++++++++++++++++++---------------- 1 file changed, 47 insertions(+), 26 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ea95b0815..26d6f28793 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2685,6 +2685,36 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +/* Called after a change to any of TTBR*_EL1 or TTBCR_EL1. */ +static void update_lpae_el1_asid(CPUARMState *env, int secure) +{ + CPUState *cs =3D CPU(arm_env_get_cpu(env)); + uint64_t ttbr0, ttbr1, ttcr; + int asid, idxmask; + + switch (secure) { + case ARM_CP_SECSTATE_S: + ttbr0 =3D env->cp15.ttbr0_s; + ttbr1 =3D env->cp15.ttbr1_s; + ttcr =3D env->cp15.tcr_el[3].raw_tcr; + /* Note that cp15.ttbr0_s =3D=3D cp15.ttbr0_el[3], so S1E3 is affe= cted. */ + /* ??? Secure EL3 really using the ASID field? Doesn't make sense= . */ + idxmask =3D ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0 | ARMMMUIdxBit= _S1E3; + break; + case ARM_CP_SECSTATE_NS: + ttbr0 =3D env->cp15.ttbr0_ns; + ttbr1 =3D env->cp15.ttbr1_ns; + ttcr =3D env->cp15.tcr_el[1].raw_tcr; + idxmask =3D ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + break; + default: + g_assert_not_reached(); + } + asid =3D extract64(ttcr & TTBCR_A1 ? ttbr1 : ttbr0, 48, 16); + + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); +} + static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2721,15 +2751,11 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - - if (arm_feature(env, ARM_FEATURE_LPAE)) { - /* With LPAE the TTBCR could result in a change of ASID - * via the TTBCR.A1 bit, so do a TLB flush. - */ - tlb_flush(CPU(cpu)); - } vmsa_ttbcr_raw_write(env, ri, value); + if (arm_feature(env, ARM_FEATURE_LPAE)) { + /* The A1 bit controls which ASID is active. */ + update_lpae_el1_asid(env, ri->secure); + } } =20 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2747,24 +2773,19 @@ static void vmsa_ttbcr_reset(CPUARMState *env, cons= t ARMCPRegInfo *ri) static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - TCR *tcr =3D raw_ptr(env, ri); - - /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ - tlb_flush(CPU(cpu)); - tcr->raw_tcr =3D value; + raw_write(env, ri, value); + /* The A1 bit controls which ASID is active. */ + update_lpae_el1_asid(env, ri->secure); } =20 -static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void vmsa_ttbr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { - /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ - if (cpreg_field_is_64bit(ri) && - extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - tlb_flush(CPU(cpu)); - } raw_write(env, ri, value); + if (cpreg_field_is_64bit(ri)) { + /* The LPAE format (64-bit write) contains an ASID field. */ + update_lpae_el1_asid(env, ri->secure); + } } =20 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2810,12 +2831,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr_el1_write, .resetvalue = =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr_el1_write, .resetvalue = =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, @@ -3067,12 +3088,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_el1_write, }, { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_el1_write, }, REGINFO_SENTINEL }; =20 --=20 2.17.2