From nobody Thu Nov 6 10:18:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540829544444895.8555411544124; Mon, 29 Oct 2018 09:12:24 -0700 (PDT) Received: from localhost ([::1]:46549 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHA9O-0008Gz-Uv for importer@patchew.org; Mon, 29 Oct 2018 12:12:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47102) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9rV-0000PZ-RF for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9rP-0000WD-Iv for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:51 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:44576) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gH9rP-0000U6-8k for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:47 -0400 Received: by mail-wr1-x442.google.com with SMTP id d17-v6so8962685wre.11 for ; Mon, 29 Oct 2018 08:53:47 -0700 (PDT) Received: from cloudburst.twiddle.net ([5.148.65.242]) by smtp.gmail.com with ESMTPSA id p3-v6sm4700517wre.47.2018.10.29.08.53.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Oct 2018 08:53:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ofW9rKlToEGgulKz6q9bEJLUs9ZXbCG+K9mtqCMjb4o=; b=YpOEZXCDccxplx7tP5i+6Q460lUctyOYHwmP2oUgx5C5F6uI7Z5TrFaK2nUQ5PRCxq WKuBaK+jY58eW6Qt0cWGHWdueIPsM+OaXG7OtJ6PjAfqY5VYDS/DtR/XRaZE4UvAwrhs gPdsg9Ge5BviJ6tpsurGimtK4yQLLEQQDNJok= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ofW9rKlToEGgulKz6q9bEJLUs9ZXbCG+K9mtqCMjb4o=; b=DzpPlHJyDorJw0dia3EqK3HiWJfkKEhoThV8OwQ8Jrwebe9xYJjI85a11f1OwwasxZ pZ/L3ZaT5jj1rROsW1U7e3+QBioS2+WLkoi5CSc+IXLNYgQlwAOiFf4a3qODfiN/o4ul +Tns46AtdeD6Oiu9io88KlzRSpgmOuM8IVuhMPkZiPkGNUikh/vvVaKbpL6b5NUY9WOJ HiCaTrG3TkpBMDH5ytxCYDEwez+ROSF4Ndr6euGiIkHdG9DRm0Tbh8CCGP8h96nbi2KF 7sjy9Va1CTrr2xDUBWBEtLLqHmUcOeQMPizmFGhHrCrK/gOxCmQwXIXZYzJeaUdA4KsM 5Hqw== X-Gm-Message-State: AGRZ1gIXkJSs54BLSzvth3yWv/l6tdk0U779VN65TkDmctuj8TlPyBpt RRDROyxXcXNUxjc8T3EXoA2H8pBT60g= X-Google-Smtp-Source: AJdET5d27sbXfiG1QP5nqyLn+zVwLuKEYCm031nwbd2m7nWtV0IagmhZ3lamsdmYiar/prezdAytFQ== X-Received: by 2002:adf:81a3:: with SMTP id 32-v6mr14056623wra.10.1540828425304; Mon, 29 Oct 2018 08:53:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 15:53:36 +0000 Message-Id: <20181029155339.15280-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181029155339.15280-1-richard.henderson@linaro.org> References: <20181029155339.15280-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 1/4] cputlb: Add tlb_set_asid_for_mmuidx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Although we can't do much with ASIDs except remember them, this will allow cleanups within target/ that should make things clearer. Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- include/exec/cpu-defs.h | 2 ++ include/exec/exec-all.h | 19 +++++++++++++++++++ accel/tcg/cputlb.c | 23 +++++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 6a60f94a41..8fbfe8c8e2 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -152,6 +152,8 @@ typedef struct CPUTLBDesc { target_ulong large_page_mask; /* The next index to use in the tlb victim table. */ size_t vindex; + /* The current ASID for this tlb. */ + uint32_t asid; } CPUTLBDesc; =20 /* diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 815e5b1e83..478f488704 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -226,6 +226,21 @@ void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint1= 6_t idxmap); * depend on when the guests translation ends the TB. */ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); +/** + * tlb_set_asid_for_mmuidx: + * @cpu: Originating cpu + * @asid: Address Space Identifier + * @idxmap: bitmap of MMU indicies to set to @asid + * @depmap: bitmap of dependent MMU indicies + * + * Set an ASID for all of @idxmap. If any previous ASID was different, + * then we may flush the mmu idx. If a flush is required, then also flush + * all dependent mmu indicies in @depmap. This latter is typically used + * for secondary page resolution, for implementing virtualization within + * the guest. + */ +void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, + uint16_t idxmap, uint16_t dep_idxmap); /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for @@ -311,6 +326,10 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced= (CPUState *cpu, uint16_t idxmap) { } +static inline void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, + uint16_t idxmap, uint16_t depma= p) +{ +} #endif =20 #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index af6bd8ccf9..60b3dc2de3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -360,6 +360,29 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, tar= get_ulong addr) tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } =20 +void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxmap, + uint16_t depmap) +{ + CPUArchState *env =3D cpu->env_ptr; + uint16_t work, to_flush =3D 0; + + /* + * We don't support ASIDs except for trivially. + * If there is any change, then we must flush the TLB. + */ + for (work =3D idxmap; work !=3D 0; work &=3D work - 1) { + int mmu_idx =3D ctz32(work); + if (env->tlb_d[mmu_idx].asid !=3D asid) { + env->tlb_d[mmu_idx].asid =3D asid; + to_flush =3D idxmap; + } + } + if (to_flush) { + to_flush |=3D depmap; + tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(to_flush)); + } +} + /* update the TLBs so that writes to code in the virtual page 'addr' can be detected */ void tlb_protect_code(ram_addr_t ram_addr) --=20 2.17.2 From nobody Thu Nov 6 10:18:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15408296956354.820355561770953; Mon, 29 Oct 2018 09:14:55 -0700 (PDT) Received: from localhost ([::1]:46560 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHABq-0001sp-A3 for importer@patchew.org; Mon, 29 Oct 2018 12:14:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9rg-0000cg-BW for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9rX-0000cy-E1 for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:58 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41937) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gH9rT-0000WP-Tr for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:52 -0400 Received: by mail-wr1-x42f.google.com with SMTP id x12-v6so9251049wrw.8 for ; Mon, 29 Oct 2018 08:53:48 -0700 (PDT) Received: from cloudburst.twiddle.net ([5.148.65.242]) by smtp.gmail.com with ESMTPSA id p3-v6sm4700517wre.47.2018.10.29.08.53.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Oct 2018 08:53:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AmAE+SggdeN2sPEPO0MNGARzD23BTp2OLLKQlCsNsjA=; b=Yr43/tx4JjmieotNR6WJZlTQ3skSzIidj5lLSDVTmU7ALXPkicDDstdC7aap9z4sjl 1+Y7VQBok+EWvbVc08S1V+Eaq9qT8eW1IiGZo1VXBEZuacdkw0S0yNSEtdRfzZanr7nd rFKbqlcfYb6E9Tdfhly4571s8pV+f/GlTXVjU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AmAE+SggdeN2sPEPO0MNGARzD23BTp2OLLKQlCsNsjA=; b=FA1RX9r3Zch/6OuWzmFxJ+j/Y4lBficfOrKU6mHVSL6CqHouExDw48oHXlF8aptYDe ar0VmokRG3mXgyUeUbKNk0c7qQNXuhWmiZKjiG9tdyDDUQsb08GKtpLUh1Scua/NbJtn kkUDbGeswq5jRuzoRhTsTKp6rmS2ALbSzNp1hVwXrRPkzCDlEVg5LXWUK5W1MXk91Nkq sNiMiaNCn26JLqUaRTNmmWr2X4LMn2yKNJxDJf1yNgE58McOOW6e6lkjeq4worJnLb7H CSTNYmlk3c7gIXARA5qXZ3hE40n4CJr4I3MRssDlljRbeyi5/vXSLD/DoPRsiROX0dIQ L2kQ== X-Gm-Message-State: AGRZ1gIfeVuaocmn+NJiI1xYhkQ1f7uH49xGs0tYKznHZFVTi/qV1UuC aRJJ+9OVgD/epQ8htACY4aX/pvFuxsM= X-Google-Smtp-Source: AJdET5cfGd11wyC1NPisyuuHx/mhWcCUC4sutpow4Kfaob/VVirbAUAlYXSZJZ5XGpQdMeVuz9vANA== X-Received: by 2002:adf:f712:: with SMTP id r18-v6mr14948203wrp.85.1540828426978; Mon, 29 Oct 2018 08:53:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 15:53:37 +0000 Message-Id: <20181029155339.15280-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181029155339.15280-1-richard.henderson@linaro.org> References: <20181029155339.15280-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PATCH 2/4] target/arm: Install ASIDs for long-form from EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In addition to providing the core with the current ASID, this minimizes both the number of flushes due to non-changing ASID as well as the set of mmu_idx that are affected by each flush. In particular, updates to the secure mode registers flushes only the relevant secure mode mmu_idx's, and similarly non-secure updates only affect non-secure mmu_idx's. Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- target/arm/helper.c | 73 +++++++++++++++++++++++++++++---------------- 1 file changed, 47 insertions(+), 26 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ea95b0815..26d6f28793 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2685,6 +2685,36 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +/* Called after a change to any of TTBR*_EL1 or TTBCR_EL1. */ +static void update_lpae_el1_asid(CPUARMState *env, int secure) +{ + CPUState *cs =3D CPU(arm_env_get_cpu(env)); + uint64_t ttbr0, ttbr1, ttcr; + int asid, idxmask; + + switch (secure) { + case ARM_CP_SECSTATE_S: + ttbr0 =3D env->cp15.ttbr0_s; + ttbr1 =3D env->cp15.ttbr1_s; + ttcr =3D env->cp15.tcr_el[3].raw_tcr; + /* Note that cp15.ttbr0_s =3D=3D cp15.ttbr0_el[3], so S1E3 is affe= cted. */ + /* ??? Secure EL3 really using the ASID field? Doesn't make sense= . */ + idxmask =3D ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0 | ARMMMUIdxBit= _S1E3; + break; + case ARM_CP_SECSTATE_NS: + ttbr0 =3D env->cp15.ttbr0_ns; + ttbr1 =3D env->cp15.ttbr1_ns; + ttcr =3D env->cp15.tcr_el[1].raw_tcr; + idxmask =3D ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + break; + default: + g_assert_not_reached(); + } + asid =3D extract64(ttcr & TTBCR_A1 ? ttbr1 : ttbr0, 48, 16); + + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); +} + static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2721,15 +2751,11 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - - if (arm_feature(env, ARM_FEATURE_LPAE)) { - /* With LPAE the TTBCR could result in a change of ASID - * via the TTBCR.A1 bit, so do a TLB flush. - */ - tlb_flush(CPU(cpu)); - } vmsa_ttbcr_raw_write(env, ri, value); + if (arm_feature(env, ARM_FEATURE_LPAE)) { + /* The A1 bit controls which ASID is active. */ + update_lpae_el1_asid(env, ri->secure); + } } =20 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2747,24 +2773,19 @@ static void vmsa_ttbcr_reset(CPUARMState *env, cons= t ARMCPRegInfo *ri) static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - TCR *tcr =3D raw_ptr(env, ri); - - /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ - tlb_flush(CPU(cpu)); - tcr->raw_tcr =3D value; + raw_write(env, ri, value); + /* The A1 bit controls which ASID is active. */ + update_lpae_el1_asid(env, ri->secure); } =20 -static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void vmsa_ttbr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { - /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ - if (cpreg_field_is_64bit(ri) && - extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - tlb_flush(CPU(cpu)); - } raw_write(env, ri, value); + if (cpreg_field_is_64bit(ri)) { + /* The LPAE format (64-bit write) contains an ASID field. */ + update_lpae_el1_asid(env, ri->secure); + } } =20 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2810,12 +2831,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr_el1_write, .resetvalue = =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr_el1_write, .resetvalue = =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, @@ -3067,12 +3088,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_el1_write, }, { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_el1_write, }, REGINFO_SENTINEL }; =20 --=20 2.17.2 From nobody Thu Nov 6 10:18:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540830764375471.4535150951681; Mon, 29 Oct 2018 09:32:44 -0700 (PDT) Received: from localhost ([::1]:46739 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHASz-0005z2-SG for importer@patchew.org; Mon, 29 Oct 2018 12:32:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47173) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9rk-0000gI-TM for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9re-0000in-Gv for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:05 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:33163) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gH9rX-0000Xh-Cx for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:57 -0400 Received: by mail-wr1-x443.google.com with SMTP id u1-v6so9295862wrn.0 for ; Mon, 29 Oct 2018 08:53:50 -0700 (PDT) Received: from cloudburst.twiddle.net ([5.148.65.242]) by smtp.gmail.com with ESMTPSA id p3-v6sm4700517wre.47.2018.10.29.08.53.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Oct 2018 08:53:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ufjQzo+SI6PyAb64orKIBD88Q1YJp7NUSWPWGJqPOn4=; b=Oo+yuyFvZwr7PLQVKIFhdYqNIUdgiB1UnEkCk2Cxjp7fKepzW4i/2RLYyOy+vWYmIS Z/pPgeNPPVdEg2K8d56y6aqRlVzh27xRq5Co/epQeq+lCMHX/BTwUiJlIcNz3+XMxGdR 3sevnYGfDe6Bwhf+7YbFGNIykiv4wSmUBKLLI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ufjQzo+SI6PyAb64orKIBD88Q1YJp7NUSWPWGJqPOn4=; b=Cu2Z9hdssmQ7kMF5J4NgLh7xjuqG+7wD0AXf+RhqdaY9AxnoANiA6FdtPqX+OPgYeA R5aJm3S1rCOMLYKpZdggPXnR+Ze9moI1aORdbSX1TDU9BM4rMSPbXPeAw7Evv/+mkKF4 VACO4gp7QhcMPYrzp2vbcZt+65gd5OJKWlA6ucw+zqkC8JnNpvch6isgWGr9uEOaWerJ 4RS6yuP9cTiB6Vg2J40ioDk+hd3Bpyp9WGYoILqZnhvCTA1I5Lq8JRSfiBdtsDevnUlD F18d7cVWM2P5FFwy9I4+FxpCBIhm+VHRVCr8XwD/5wXZeY8Q65ao0ToqoPqje9JymSdX o2Ww== X-Gm-Message-State: AGRZ1gITt1Xsr1tdLkKc8ScCuT2YlMInbxDMxbANUwyrj89uKDa5EHG+ KV2j/RWyoiGCvXIZqPtLiFupt2csUcQ= X-Google-Smtp-Source: AJdET5f0P3FJUMbxICTLdHbCeMvTuM8NbuyslzRrMGtrQqzUoZTsns2BQZ0LqSeKESU7ne+6Jbt1pg== X-Received: by 2002:adf:ca03:: with SMTP id o3-v6mr4998017wrh.148.1540828428616; Mon, 29 Oct 2018 08:53:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 15:53:38 +0000 Message-Id: <20181029155339.15280-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181029155339.15280-1-richard.henderson@linaro.org> References: <20181029155339.15280-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 3/4] target/arm: Install ASIDs for short-form from EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is less complex than the LPAE case, but still we now avoid the flush in case it is only the PROCID field that is changing. Signed-off-by: Richard Henderson Tested-by: Emilio G. Cota --- target/arm/helper.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 26d6f28793..f767467dcf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -541,17 +541,31 @@ static void fcse_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - - if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) - && !extended_addresses_enabled(env)) { - /* For VMSA (when not using the LPAE long descriptor page table - * format) this register includes the ASID, so do a TLB flush. - * For PMSA it is purely a process ID and no action is needed. - */ - tlb_flush(CPU(cpu)); - } raw_write(env, ri, value); + + /* + * For VMSA (when not using the LPAE long descriptor page table format) + * this register includes the ASID. For PMSA it is purely a process ID + * and no action is needed. + */ + if (!arm_feature(env, ARM_FEATURE_PMSA) && + !extended_addresses_enabled(env)) { + CPUState *cs =3D CPU(arm_env_get_cpu(env)); + int asid =3D extract32(value, 0, 8); + int idxmask; + + switch (ri->secure) { + case ARM_CP_SECSTATE_S: + idxmask =3D ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + break; + case ARM_CP_SECSTATE_NS: + idxmask =3D ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + break; + default: + g_assert_not_reached(); + } + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); + } } =20 /* IS variants of TLB operations must affect all cores */ --=20 2.17.2 From nobody Thu Nov 6 10:18:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540829849995179.23470612860274; Mon, 29 Oct 2018 09:17:29 -0700 (PDT) Received: from localhost ([::1]:46588 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gHAEG-0004lM-AD for importer@patchew.org; Mon, 29 Oct 2018 12:17:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47172) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gH9rk-0000gH-TO for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gH9rb-0000gK-Ga for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:54:05 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:34100) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gH9rV-0000Yg-QH for qemu-devel@nongnu.org; Mon, 29 Oct 2018 11:53:55 -0400 Received: by mail-wr1-x444.google.com with SMTP id l6-v6so9278733wrt.1 for ; Mon, 29 Oct 2018 08:53:51 -0700 (PDT) Received: from cloudburst.twiddle.net ([5.148.65.242]) by smtp.gmail.com with ESMTPSA id p3-v6sm4700517wre.47.2018.10.29.08.53.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Oct 2018 08:53:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LZQNZ6rcVxWOWRYJTTswlGPMH894sJFeWGghPgY04yI=; b=hqhWDH5bd9BtnniyXouzhL/u9ulvDM23+tT3KBJelBICF3HTKQIl+fZvjEqT+MhNeN jSHwNkw95O1PMakzAETobdzPQGLb5bPwR5CjdLQ8noAcsM1/gwUDq13zCABEi2vNkx69 hS0iL0lDwgBMlEfBHyX4VeKWjjl4uwILRERBM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LZQNZ6rcVxWOWRYJTTswlGPMH894sJFeWGghPgY04yI=; b=r8638DRvlqbibedO96j2mr0xTKXmhqTtNkTENeYBo1RbKOTq6FHTzCz0gWtngmCYkl KKfN7Rww3e07q2Z6V8wwxZajsq5SYNyhpuXk+yKTASRbOvSt17FAfvvsi/6y91dorTmm 9ucXATp0gTzg9EwAWh8FfXVzLBaCUqiroLYJRYPfvl+m3fpOFWTmpnnrY04Z7nMDttgF fSjwZsEsIQD5bGhiPpgkJttbs0BAfmemsPX7CHteH0czosW4byFe/stJXvr/BeCPtdjB u9Z1syKVfzDXeZ07DtQgfCo1Jxo2XOqSrxoyZ9WR6jAI+F2dvyFrcXo2C9rjrsD1TGhz fxEg== X-Gm-Message-State: AGRZ1gKRD01zOwRMEzz/mokKX21n0DDhBjmI4n7Xh7f8hhFjxpmvmbGa 12A3dDZXkn1X51Ol1CycaGq/Ia5vSQM= X-Google-Smtp-Source: AJdET5cpT1K7uc9hw1/YYEVHzGq+afJmaNdT/XlzJ9AMGfkQGQ+lMfFsH5s41O0AH1s5Eu4O/IXgdQ== X-Received: by 2002:adf:bf10:: with SMTP id p16-v6mr14431007wrh.235.1540828429538; Mon, 29 Oct 2018 08:53:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2018 15:53:39 +0000 Message-Id: <20181029155339.15280-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181029155339.15280-1-richard.henderson@linaro.org> References: <20181029155339.15280-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 4/4] target/arm: Install ASIDs for EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The VMID is the ASID for the 2nd stage page lookup. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Tested-by: Emilio G. Cota --- target/arm/helper.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f767467dcf..4b14f2c05b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2805,17 +2805,23 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D CPU(arm_env_get_cpu(env)); + int vmid; =20 - /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ - if (raw_read(env, ri) !=3D value) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - raw_write(env, ri, value); - } + raw_write(env, ri, value); + + /* + * TODO: with ARMv8.1-VMID16, aarch64 must examine VTCR.VS + * (re-evaluating with changes to VTCR) then use bits [63:48]. + */ + vmid =3D extract64(value, 48, 8); + + /* + * A change in VMID to the stage2 page table (S2NS) invalidates + * the combined stage 1&2 tlbs (S12NSE1 and S12NSE0). + */ + tlb_set_asid_for_mmuidx(cs, vmid, ARMMMUIdxBit_S2NS, + ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0); } =20 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { --=20 2.17.2