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Cota" To: qemu-devel@nongnu.org Date: Thu, 25 Oct 2018 13:20:34 -0400 Message-Id: <20181025172057.20414-26-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181025172057.20414-1-cota@braap.org> References: <20181025172057.20414-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC 25/48] target/arm: prepare for 2-pass translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Pavel Dovgalyuk , Stefan Hajnoczi Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Emilio G. Cota --- target/arm/translate-a64.c | 8 ++++++-- target/arm/translate.c | 25 +++++++++++++++++++++---- 2 files changed, 27 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8b1e20dd59..dab5f6efd3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13783,11 +13783,13 @@ static void disas_data_proc_simd_fp(DisasContext = *s, uint32_t insn) } =20 /* C3.1 A64 instruction index by encoding */ -static void disas_a64_insn(CPUARMState *env, DisasContext *s) +static void disas_a64_insn(CPUARMState *env, DisasContext *s, + struct qemu_plugin_insn *plugin_insn) { uint32_t insn; =20 insn =3D arm_ldl_code(env, s->pc, s->sctlr_b); + qemu_plugin_insn_append(plugin_insn, &insn, sizeof(insn)); s->insn =3D insn; s->pc +=3D 4; =20 @@ -13959,7 +13961,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu, default_exception_el(dc)); dc->base.is_jmp =3D DISAS_NORETURN; } else { - disas_a64_insn(env, dc); + disas_a64_insn(env, dc, plugin_insn); } =20 dc->base.pc_next =3D dc->pc; @@ -14058,4 +14060,6 @@ const TranslatorOps aarch64_translator_ops =3D { .translate_insn =3D aarch64_tr_translate_insn, .tb_stop =3D aarch64_tr_tb_stop, .disas_log =3D aarch64_tr_disas_log, + .ctx_base_offset =3D offsetof(DisasContext, base), + .ctx_size =3D sizeof(DisasContext), }; diff --git a/target/arm/translate.c b/target/arm/translate.c index 2fd32a2684..015153a260 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10198,7 +10198,8 @@ gen_thumb2_data_op(DisasContext *s, int op, int con= ds, uint32_t shifter_out, } =20 /* Translate a 32-bit thumb instruction. */ -static void disas_thumb2_insn(DisasContext *s, uint32_t insn) +static void disas_thumb2_insn(DisasContext *s, uint32_t insn, + struct qemu_plugin_insn *plugin_insn) { uint32_t imm, shift, offset; uint32_t rd, rn, rm, rs; @@ -11736,7 +11737,8 @@ illegal_op: default_exception_el(s)); } =20 -static void disas_thumb_insn(DisasContext *s, uint32_t insn) +static void disas_thumb_insn(DisasContext *s, uint32_t insn, + struct qemu_plugin_insn *plugin_insn) { uint32_t val, op, rm, rn, rd, shift, cond; int32_t offset; @@ -12800,6 +12802,7 @@ static void arm_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu, =20 insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); dc->insn =3D insn; + qemu_plugin_insn_append(plugin_insn, &insn, sizeof(insn)); dc->pc +=3D 4; disas_arm_insn(dc, insn); =20 @@ -12870,11 +12873,21 @@ static void thumb_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu, insn =3D arm_lduw_code(env, dc->pc, dc->sctlr_b); is_16bit =3D thumb_insn_is_16bit(dc, insn); dc->pc +=3D 2; + if (plugin_insn) { + uint16_t insn16 =3D insn; + + qemu_plugin_insn_append(plugin_insn, &insn16, sizeof(insn16)); + } if (!is_16bit) { uint32_t insn2 =3D arm_lduw_code(env, dc->pc, dc->sctlr_b); =20 insn =3D insn << 16 | insn2; dc->pc +=3D 2; + if (plugin_insn) { + uint16_t insn16 =3D insn2; + + qemu_plugin_insn_append(plugin_insn, &insn16, sizeof(insn16)); + } } dc->insn =3D insn; =20 @@ -12887,9 +12900,9 @@ static void thumb_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu, } =20 if (is_16bit) { - disas_thumb_insn(dc, insn); + disas_thumb_insn(dc, insn, plugin_insn); } else { - disas_thumb2_insn(dc, insn); + disas_thumb2_insn(dc, insn, plugin_insn); } =20 /* Advance the Thumb condexec condition. */ @@ -13064,6 +13077,8 @@ static const TranslatorOps arm_translator_ops =3D { .translate_insn =3D arm_tr_translate_insn, .tb_stop =3D arm_tr_tb_stop, .disas_log =3D arm_tr_disas_log, + .ctx_base_offset =3D offsetof(DisasContext, base), + .ctx_size =3D sizeof(DisasContext), }; =20 static const TranslatorOps thumb_translator_ops =3D { @@ -13074,6 +13089,8 @@ static const TranslatorOps thumb_translator_ops =3D= { .translate_insn =3D thumb_tr_translate_insn, .tb_stop =3D arm_tr_tb_stop, .disas_log =3D arm_tr_disas_log, + .ctx_base_offset =3D offsetof(DisasContext, base), + .ctx_size =3D sizeof(DisasContext), }; =20 /* generate intermediate code for basic block 'tb'. */ --=20 2.17.1