From nobody Thu Nov 6 10:33:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154042931270715.432353529398824; Wed, 24 Oct 2018 18:01:52 -0700 (PDT) Received: from localhost ([::1]:51493 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFU23-0001sC-J1 for importer@patchew.org; Wed, 24 Oct 2018 21:01:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFTv5-0003wb-Qv for qemu-devel@nongnu.org; Wed, 24 Oct 2018 20:54:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFTv2-0006Kb-0d for qemu-devel@nongnu.org; Wed, 24 Oct 2018 20:54:39 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59366) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gFTuy-0006AD-Rv for qemu-devel@nongnu.org; Wed, 24 Oct 2018 20:54:35 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 79ABB356D5; Thu, 25 Oct 2018 00:54:28 +0000 (UTC) Received: from redhat.com (ovpn-120-69.rdu2.redhat.com [10.10.120.69]) by smtp.corp.redhat.com (Postfix) with SMTP id 437B71054FBB; Thu, 25 Oct 2018 00:54:21 +0000 (UTC) Date: Wed, 24 Oct 2018 20:54:20 -0400 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <20181025005110.249256-19-mst@redhat.com> References: <20181025005110.249256-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20181025005110.249256-1-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Thu, 25 Oct 2018 00:54:28 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL v2 18/28] hw/pci-host/x86: extract get_pci_hole64_start_value() helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alex Williamson , Gerd Hoffmann , Igor Mammedov , Laszlo Ersek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laszlo Ersek Expose the calculated "hole64 start" GPAs as plain uint64_t values, extracting the internals of the current property getters. This patch doesn't change behavior. Cc: "Michael S. Tsirkin" Cc: Alex Williamson Cc: Gerd Hoffmann Cc: Igor Mammedov Cc: Marcel Apfelbaum Signed-off-by: Laszlo Ersek Reviewed-by: Marcel Apfelbaum Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/pci-host/piix.c | 15 +++++++++++---- hw/pci-host/q35.c | 15 +++++++++++---- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index da73743fa2..15cc34912e 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -249,9 +249,7 @@ static void i440fx_pcihost_get_pci_hole_end(Object *obj= , Visitor *v, * the 64bit PCI hole will start after "over 4G RAM" and the * reserved space for memory hotplug if any. */ -static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, - const char *name, - void *opaque, Error **errp) +static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj) { PCIHostState *h =3D PCI_HOST_BRIDGE(obj); I440FXState *s =3D I440FX_PCI_HOST_BRIDGE(obj); @@ -263,7 +261,16 @@ static void i440fx_pcihost_get_pci_hole64_start(Object= *obj, Visitor *v, if (!value && s->pci_hole64_fix) { value =3D pc_pci_hole64_start(); } - visit_type_uint64(v, name, &value, errp); + return value; +} + +static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + uint64_t hole64_start =3D i440fx_pcihost_get_pci_hole64_start_value(ob= j); + + visit_type_uint64(v, name, &hole64_start, errp); } =20 /* diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 8ce1e09932..919de104fc 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -113,9 +113,7 @@ static void q35_host_get_pci_hole_end(Object *obj, Visi= tor *v, * the 64bit PCI hole will start after "over 4G RAM" and the * reserved space for memory hotplug if any. */ -static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, - const char *name, void *opaque, - Error **errp) +static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) { PCIHostState *h =3D PCI_HOST_BRIDGE(obj); Q35PCIHost *s =3D Q35_HOST_DEVICE(obj); @@ -127,7 +125,16 @@ static void q35_host_get_pci_hole64_start(Object *obj,= Visitor *v, if (!value && s->pci_hole64_fix) { value =3D pc_pci_hole64_start(); } - visit_type_uint64(v, name, &value, errp); + return value; +} + +static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint64_t hole64_start =3D q35_host_get_pci_hole64_start_value(obj); + + visit_type_uint64(v, name, &hole64_start, errp); } =20 /* --=20 MST