From nobody Sat Apr 27 18:11:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540428927109223.9577085052822; Wed, 24 Oct 2018 17:55:27 -0700 (PDT) Received: from localhost ([::1]:51435 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFTvp-00045X-K0 for importer@patchew.org; Wed, 24 Oct 2018 20:55:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57459) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFTrv-0000X8-BT for qemu-devel@nongnu.org; Wed, 24 Oct 2018 20:51:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFTrs-0000y3-R7 for qemu-devel@nongnu.org; Wed, 24 Oct 2018 20:51:23 -0400 Received: from smtp36.i.mail.ru ([94.100.177.96]:50252) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gFTrs-0000wg-BE for qemu-devel@nongnu.org; Wed, 24 Oct 2018 20:51:20 -0400 Received: by smtp36.i.mail.ru with esmtpa (envelope-from ) id 1gFTrq-0003wB-9C; Thu, 25 Oct 2018 03:51:18 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=Hhj0U0SsV9Bn0TLydswyCq1CSGYgP4a4sJ+jsIiIwQI=; b=tAfDCyfPiz9vJTPfYiBy6WwbD/AQijvnv//4E9DbVgXNju8muHLwMKWuXFYxdeTbUA/ILe/7WNMVAIlm0B00NkRX4VuGz6zdxTXc/8IgjiteHj6M/94/nQt8acIgrbK3UpKIWQ/WoN36UnlyCPS+FY+wkh5GApWMAOpgie8PLeE=; To: qemu-devel@nongnu.org Date: Thu, 25 Oct 2018 03:50:50 +0300 Message-Id: <20181025005052.27661-2-jusual@mail.ru> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181025005052.27661-1-jusual@mail.ru> References: <20181025005052.27661-1-jusual@mail.ru> Authentication-Results: smtp36.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-77F55803: JXxPhqsJyJw1KMqRCIZqBCfsOFW6Z55IGvRu1iUT3/FlINBPUhsl/Q== X-7FA49CB5: 0D63561A33F958A53F4D8545FEEB90732A643B03C4E8136AB5BAB125A1B80CD38941B15DA834481FA18204E546F3947CEDCF5861DED71B2F389733CBF5DBD5E9C8A9BA7A39EFB7666BA297DBC24807EA117882F44604297287769387670735209ECD01F8117BC8BEA471835C12D1D977C4224003CC8364767815B9869FA544D8090A508E0FED6299176DF2183F8FC7C003F1AB874ED89028E0C89D67371282C4A18204E546F3947CAD74539164518AE5BA3038C0950A5D36581343779C53C132BD4B6F7A4D31EC0B7815B9869FA544D8EC76A7562686271E6BA297DBC24807EA089D37D7C0E48F6C8AA50765F7900637E138BF1728713E35A1335D6E25872102089D37D7C0E48F6C5571747095F342E857739F23D657EF2B6825BDBE14D8E70237733D48D1BA725CBD9CCCA9EDD067B1EDA766A37F9254B7 X-Mailru-Sender: 488F1D93D47396381C630131DEB70813C2F2AA22CF127C4BBC7E2787549EB3DDCD254E74BFB65C42F47EA7097ACE9B7FFB559BB5D741EB963BB91581D3AD5D250F2DC73CC0BFB1A30DA7A0AF5A3A8387 X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 94.100.177.96 Subject: [Qemu-devel] [PATCH v3 1/3] hw/char: Implement nRF51 SoC UART X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Thomas Huth , Joel Stanley , Stefan Hajnoczi , Paolo Bonzini , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Not implemented: CTS/NCTS, PSEL*. Signed-off-by: Julia Suvorova Reviewed-by: Stefan Hajnoczi --- hw/char/Makefile.objs | 1 + hw/char/nrf51_uart.c | 330 +++++++++++++++++++++++++++++++++++ hw/char/trace-events | 4 + include/hw/char/nrf51_uart.h | 78 +++++++++ 4 files changed, 413 insertions(+) create mode 100644 hw/char/nrf51_uart.c create mode 100644 include/hw/char/nrf51_uart.h diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index b570531291..c4947d7ae7 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -1,5 +1,6 @@ common-obj-$(CONFIG_IPACK) +=3D ipoctal232.o common-obj-$(CONFIG_ESCC) +=3D escc.o +common-obj-$(CONFIG_NRF51_SOC) +=3D nrf51_uart.o common-obj-$(CONFIG_PARALLEL) +=3D parallel.o common-obj-$(CONFIG_PARALLEL) +=3D parallel-isa.o common-obj-$(CONFIG_PL011) +=3D pl011.o diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c new file mode 100644 index 0000000000..2f5fae6167 --- /dev/null +++ b/hw/char/nrf51_uart.c @@ -0,0 +1,330 @@ +/* + * nRF51 SoC UART emulation + * + * See nRF51 Series Reference Manual, "29 Universal Asynchronous + * Receiver/Transmitter" for hardware specifications: + * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * + * Copyright (c) 2018 Julia Suvorova + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/char/nrf51_uart.h" +#include "trace.h" + +static void nrf51_uart_update_irq(NRF51UARTState *s) +{ + bool irq =3D false; + + irq |=3D (s->reg[R_UART_RXDRDY] && + (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK)); + irq |=3D (s->reg[R_UART_TXDRDY] && + (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK)); + irq |=3D (s->reg[R_UART_ERROR] && + (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK)); + irq |=3D (s->reg[R_UART_RXTO] && + (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK)); + + qemu_set_irq(s->irq, irq); +} + +static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + uint64_t r; + + if (!s->enabled) { + return 0; + } + + switch (addr) { + case A_UART_RXD: + r =3D s->rx_fifo[s->rx_fifo_pos]; + if (s->rx_started && s->rx_fifo_len) { + s->rx_fifo_pos =3D (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH; + s->rx_fifo_len--; + if (s->rx_fifo_len) { + s->reg[R_UART_RXDRDY] =3D 1; + nrf51_uart_update_irq(s); + } + qemu_chr_fe_accept_input(&s->chr); + } + break; + case A_UART_INTENSET: + case A_UART_INTENCLR: + case A_UART_INTEN: + r =3D s->reg[R_UART_INTEN]; + break; + default: + r =3D s->reg[addr / 4]; + break; + } + + trace_nrf51_uart_read(addr, r, size); + + return r; +} + +static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *o= paque) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + int r; + uint8_t c =3D s->reg[R_UART_TXD]; + + s->watch_tag =3D 0; + + r =3D qemu_chr_fe_write(&s->chr, &c, 1); + if (r <=3D 0) { + s->watch_tag =3D qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HU= P, + uart_transmit, s); + if (!s->watch_tag) { + /* The hardware has no transmit error reporting, + * so silently drop the byte + */ + goto buffer_drained; + } + return FALSE; + } + +buffer_drained: + s->reg[R_UART_TXDRDY] =3D 1; + s->pending_tx_byte =3D false; + return FALSE; +} + +static void uart_cancel_transmit(NRF51UARTState *s) +{ + if (s->watch_tag) { + g_source_remove(s->watch_tag); + s->watch_tag =3D 0; + } +} + +static void uart_write(void *opaque, hwaddr addr, + uint64_t value, unsigned int size) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + + trace_nrf51_uart_write(addr, value, size); + + if (!s->enabled && (addr !=3D A_UART_ENABLE)) { + return; + } + + switch (addr) { + case A_UART_TXD: + if (!s->pending_tx_byte && s->tx_started) { + s->reg[R_UART_TXD] =3D value; + s->pending_tx_byte =3D true; + uart_transmit(NULL, G_IO_OUT, s); + } + break; + case A_UART_INTEN: + s->reg[R_UART_INTEN] =3D value; + break; + case A_UART_INTENSET: + s->reg[R_UART_INTEN] |=3D value; + break; + case A_UART_INTENCLR: + s->reg[R_UART_INTEN] &=3D ~value; + break; + case A_UART_TXDRDY ... A_UART_RXTO: + s->reg[addr / 4] =3D value; + break; + case A_UART_ERRORSRC: + s->reg[addr / 4] &=3D ~value; + break; + case A_UART_RXD: + break; + case A_UART_RXDRDY: + if (value =3D=3D 0) { + s->reg[R_UART_RXDRDY] =3D 0; + } + break; + case A_UART_STARTTX: + if (value =3D=3D 1) { + s->tx_started =3D true; + } + break; + case A_UART_STARTRX: + if (value =3D=3D 1) { + s->rx_started =3D true; + } + break; + case A_UART_ENABLE: + if (value) { + if (value =3D=3D 4) { + s->enabled =3D true; + } + break; + } + s->enabled =3D false; + value =3D 1; + /* fall through */ + case A_UART_SUSPEND: + case A_UART_STOPTX: + if (value =3D=3D 1) { + s->tx_started =3D false; + } + /* fall through */ + case A_UART_STOPRX: + if (addr !=3D A_UART_STOPTX && value =3D=3D 1) { + s->rx_started =3D false; + s->reg[R_UART_RXTO] =3D 1; + } + break; + default: + s->reg[addr / 4] =3D value; + break; + } + nrf51_uart_update_irq(s); +} + +static const MemoryRegionOps uart_ops =3D { + .read =3D uart_read, + .write =3D uart_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void nrf51_uart_reset(DeviceState *dev) +{ + NRF51UARTState *s =3D NRF51_UART(dev); + + s->pending_tx_byte =3D 0; + + uart_cancel_transmit(s); + + memset(s->reg, 0, sizeof(s->reg)); + + s->reg[R_UART_PSELRTS] =3D 0xFFFFFFFF; + s->reg[R_UART_PSELTXD] =3D 0xFFFFFFFF; + s->reg[R_UART_PSELCTS] =3D 0xFFFFFFFF; + s->reg[R_UART_PSELRXD] =3D 0xFFFFFFFF; + s->reg[R_UART_BAUDRATE] =3D 0x4000000; + + s->rx_fifo_len =3D 0; + s->rx_fifo_pos =3D 0; + s->rx_started =3D false; + s->tx_started =3D false; + s->enabled =3D false; +} + +static void uart_receive(void *opaque, const uint8_t *buf, int size) +{ + + NRF51UARTState *s =3D NRF51_UART(opaque); + int i; + + if (size =3D=3D 0 || s->rx_fifo_len >=3D UART_FIFO_LENGTH) { + return; + } + + for (i =3D 0; i < size; i++) { + uint32_t pos =3D (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LEN= GTH; + s->rx_fifo[pos] =3D buf[i]; + s->rx_fifo_len++; + } + + s->reg[R_UART_RXDRDY] =3D 1; + nrf51_uart_update_irq(s); +} + +static int uart_can_receive(void *opaque) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + + return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0; +} + +static void uart_event(void *opaque, int event) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + + if (event =3D=3D CHR_EVENT_BREAK) { + s->reg[R_UART_ERRORSRC] |=3D 3; + s->reg[R_UART_ERROR] =3D 1; + nrf51_uart_update_irq(s); + } +} + +static void nrf51_uart_realize(DeviceState *dev, Error **errp) +{ + NRF51UARTState *s =3D NRF51_UART(dev); + + qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, + uart_event, NULL, s, NULL, true); +} + +static void nrf51_uart_init(Object *obj) +{ + NRF51UARTState *s =3D NRF51_UART(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &uart_ops, s, + "nrf51_soc.uart", UART_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static int nrf51_uart_post_load(void *opaque, int version_id) +{ + NRF51UARTState *s =3D NRF51_UART(opaque); + + if (s->pending_tx_byte) { + s->watch_tag =3D qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HU= P, + uart_transmit, s); + } + + return 0; +} + +static const VMStateDescription nrf51_uart_vmstate =3D { + .name =3D "nrf51_soc.uart", + .post_load =3D nrf51_uart_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C), + VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH), + VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState), + VMSTATE_UINT32(rx_fifo_len, NRF51UARTState), + VMSTATE_BOOL(rx_started, NRF51UARTState), + VMSTATE_BOOL(tx_started, NRF51UARTState), + VMSTATE_BOOL(pending_tx_byte, NRF51UARTState), + VMSTATE_BOOL(enabled, NRF51UARTState), + VMSTATE_END_OF_LIST() + } +}; + +static Property nrf51_uart_properties[] =3D { + DEFINE_PROP_CHR("chardev", NRF51UARTState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void nrf51_uart_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D nrf51_uart_reset; + dc->realize =3D nrf51_uart_realize; + dc->props =3D nrf51_uart_properties; + dc->vmsd =3D &nrf51_uart_vmstate; +} + +static const TypeInfo nrf51_uart_info =3D { + .name =3D TYPE_NRF51_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51UARTState), + .instance_init =3D nrf51_uart_init, + .class_init =3D nrf51_uart_class_init +}; + +static void nrf51_uart_register_types(void) +{ + type_register_static(&nrf51_uart_info); +} + +type_init(nrf51_uart_register_types) diff --git a/hw/char/trace-events b/hw/char/trace-events index b64213d4dd..de34a74399 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -73,3 +73,7 @@ cmsdk_apb_uart_receive(uint8_t c) "CMSDK APB UART: got ch= aracter 0x%x from backe cmsdk_apb_uart_tx_pending(void) "CMSDK APB UART: character send to backend= pending" cmsdk_apb_uart_tx(uint8_t c) "CMSDK APB UART: character 0x%x sent to backe= nd" cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1" + +# hw/char/nrf51_uart.c +nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" P= RIx64 " value 0x%" PRIx64 " size %u" +nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0= x%" PRIx64 " value 0x%" PRIx64 " size %u" diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h new file mode 100644 index 0000000000..e3ecb7c81c --- /dev/null +++ b/include/hw/char/nrf51_uart.h @@ -0,0 +1,78 @@ +/* + * nRF51 SoC UART emulation + * + * Copyright (c) 2018 Julia Suvorova + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +#ifndef NRF51_UART_H +#define NRF51_UART_H + +#include "hw/sysbus.h" +#include "chardev/char-fe.h" +#include "hw/registerfields.h" + +#define UART_FIFO_LENGTH 6 +#define UART_BASE 0x40002000 +#define UART_SIZE 0x1000 + +#define TYPE_NRF51_UART "nrf51_soc.uart" +#define NRF51_UART(obj) OBJECT_CHECK(NRF51UARTState, (obj), TYPE_NRF51_UAR= T) + +REG32(UART_STARTRX, 0x000) +REG32(UART_STOPRX, 0x004) +REG32(UART_STARTTX, 0x008) +REG32(UART_STOPTX, 0x00C) +REG32(UART_SUSPEND, 0x01C) + +REG32(UART_CTS, 0x100) +REG32(UART_NCTS, 0x104) +REG32(UART_RXDRDY, 0x108) +REG32(UART_TXDRDY, 0x11C) +REG32(UART_ERROR, 0x124) +REG32(UART_RXTO, 0x144) + +REG32(UART_INTEN, 0x300) + FIELD(UART_INTEN, CTS, 0, 1) + FIELD(UART_INTEN, NCTS, 1, 1) + FIELD(UART_INTEN, RXDRDY, 2, 1) + FIELD(UART_INTEN, TXDRDY, 7, 1) + FIELD(UART_INTEN, ERROR, 9, 1) + FIELD(UART_INTEN, RXTO, 17, 1) +REG32(UART_INTENSET, 0x304) +REG32(UART_INTENCLR, 0x308) +REG32(UART_ERRORSRC, 0x480) +REG32(UART_ENABLE, 0x500) +REG32(UART_PSELRTS, 0x508) +REG32(UART_PSELTXD, 0x50C) +REG32(UART_PSELCTS, 0x510) +REG32(UART_PSELRXD, 0x514) +REG32(UART_RXD, 0x518) +REG32(UART_TXD, 0x51C) +REG32(UART_BAUDRATE, 0x524) +REG32(UART_CONFIG, 0x56C) + +typedef struct NRF51UARTState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + CharBackend chr; + qemu_irq irq; + guint watch_tag; + + uint8_t rx_fifo[UART_FIFO_LENGTH]; + unsigned int rx_fifo_pos; + unsigned int rx_fifo_len; + + uint32_t reg[0x56C]; + + bool rx_started; + bool tx_started; + bool pending_tx_byte; + bool enabled; +} NRF51UARTState; + +#endif --=20 2.17.1 From nobody Sat Apr 27 18:11:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540429102132459.45007932534816; Wed, 24 Oct 2018 17:58:22 -0700 (PDT) Received: from localhost ([::1]:51459 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFTyf-000749-4B for importer@patchew.org; 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X-Received-From: 94.100.177.96 Subject: [Qemu-devel] [PATCH v3 2/3] hw/arm/nrf51_soc: Connect UART to nRF51 SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Thomas Huth , Joel Stanley , Stefan Hajnoczi , Paolo Bonzini , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Wire up nRF51 UART in the corresponding SoC. Signed-off-by: Julia Suvorova Reviewed-by: Alistair Francis Reviewed-by: Stefan Hajnoczi --- hw/arm/microbit.c | 2 ++ hw/arm/nrf51_soc.c | 20 ++++++++++++++++++++ include/hw/arm/nrf51_soc.h | 3 +++ 3 files changed, 25 insertions(+) diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index e7d74116a5..a734e7f650 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -12,6 +12,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/arm/arm.h" +#include "sysemu/sysemu.h" #include "exec/address-spaces.h" =20 #include "hw/arm/nrf51_soc.h" @@ -35,6 +36,7 @@ static void microbit_init(MachineState *machine) =20 sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51), TYPE_NRF51_SOC); + qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0)); object_property_set_link(soc, OBJECT(system_memory), "memory", &error_fatal); object_property_set_bool(soc, true, "realized", &error_fatal); diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 1a59ef4552..b89c1bdea0 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -43,9 +43,12 @@ #define NRF51822_FLASH_SIZE (256 * 1024) #define NRF51822_SRAM_SIZE (16 * 1024) =20 +#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s =3D NRF51_SOC(dev_soc); + MemoryRegion *mr; Error *err =3D NULL; =20 if (!s->board_memory) { @@ -82,6 +85,18 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Erro= r **errp) } memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); =20 + /* UART */ + object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); + memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(UART_BASE))); + create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); create_unimplemented_device("nrf51_soc.private", @@ -99,6 +114,11 @@ static void nrf51_soc_init(Object *obj) qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m0")); qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); + + sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart), + TYPE_NRF51_UART); + object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", + &error_abort); } =20 static Property nrf51_soc_properties[] =3D { diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index f4e092b554..73fc92e9a8 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -12,6 +12,7 @@ =20 #include "hw/sysbus.h" #include "hw/arm/armv7m.h" +#include "hw/char/nrf51_uart.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ @@ -24,6 +25,8 @@ typedef struct NRF51State { /*< public >*/ ARMv7MState cpu; =20 + NRF51UARTState uart; + MemoryRegion iomem; MemoryRegion sram; MemoryRegion flash; --=20 2.17.1 From nobody Sat Apr 27 18:11:21 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Wed, 24 Oct 2018 20:51:32 -0400 Received: by smtp36.i.mail.ru with esmtpa (envelope-from ) id 1gFTry-0003wB-Ei; Thu, 25 Oct 2018 03:51:26 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=oR7pbe7ukcr9XLYDtarOBTK/SFIGOekoNcKRDTsoSvE=; b=J5JixtHM9jEwfnUa2aAqdTDfqg9qXvxAGgxaj02fudFQtWX3gB1eC3DHsQ+DH2TXZqL/9aVZo1vQnL2qTMrTuiA1CNzZrlC+QoPqCRbMMlsI8PLAdeWnhJGvHNUSW9xllXoYIazZ0VqX17HuQr/KPYGNDSjUvoBlRuuICL6rYps=; To: qemu-devel@nongnu.org Date: Thu, 25 Oct 2018 03:50:52 +0300 Message-Id: <20181025005052.27661-4-jusual@mail.ru> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181025005052.27661-1-jusual@mail.ru> References: <20181025005052.27661-1-jusual@mail.ru> Authentication-Results: smtp36.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-77F55803: Jgxman1ms2rvBLq7Z+PloxFa0sLaR1moD3WjDdmqoRqiGj+AsTzMcQ== X-7FA49CB5: 0D63561A33F958A5E07DE6767A38B7022A643B03C4E8136A6029A6CBD84F08EA8941B15DA834481FA18204E546F3947C062BEEFFB5F8EA3EF6B57BC7E64490618DEB871D839B7333395957E7521B51C2545D4CF71C94A83E9FA2833FD35BB23D27C277FBC8AE2E8B2EE5AD8F952D28FBA471835C12D1D977C4224003CC8364767815B9869FA544D8090A508E0FED629923F8577A6DFFEA7C7F16001415B116942E03817F3C3E88BC8594870E7945379638D4DC57D478E6886E0066C2D8992A16E0C89D67371282C4CF19DD082D7633A0E7DDDDC251EA7DABD81D268191BDAD3D4E70A05D1297E1BB35872C767BF85DA227C277FBC8AE2E8B48EBEC27BC641984370D80C21B0FD28E089D37D7C0E48F6C5571747095F342E857739F23D657EF2B6825BDBE14D8E702AA1DF4CB901976EF00306258E7E6ABB4E4A6367B16DE6309 X-Mailru-Sender: 488F1D93D47396381C630131DEB70813BEE453E5C65230BECDCA2365455661E2CD254E74BFB65C42F47EA7097ACE9B7FFB559BB5D741EB963BB91581D3AD5D250F2DC73CC0BFB1A30DA7A0AF5A3A8387 X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 94.100.177.96 Subject: [Qemu-devel] [PATCH v3 3/3] tests/boot-serial-test: Add microbit board testcase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Thomas Huth , Joel Stanley , Stefan Hajnoczi , Paolo Bonzini , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" New mini-kernel test for nRF51 SoC UART. Signed-off-by: Julia Suvorova Acked-by: Thomas Huth Reviewed-by: Stefan Hajnoczi --- tests/boot-serial-test.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c index f865822e32..8ec6aed35d 100644 --- a/tests/boot-serial-test.c +++ b/tests/boot-serial-test.c @@ -62,6 +62,24 @@ static const uint8_t kernel_aarch64[] =3D { 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */ }; =20 +static const uint8_t kernel_nrf51[] =3D { + 0x00, 0x00, 0x00, 0x00, /* Stack top address */ + 0x09, 0x00, 0x00, 0x00, /* Reset handler address */ + 0x04, 0x4a, /* ldr r2, [pc, #16] Get ENAB= LE */ + 0x04, 0x21, /* movs r1, #4 */ + 0x11, 0x60, /* str r1, [r2] */ + 0x04, 0x4a, /* ldr r2, [pc, #16] Get STAR= TTX */ + 0x01, 0x21, /* movs r1, #1 */ + 0x11, 0x60, /* str r1, [r2] */ + 0x03, 0x4a, /* ldr r2, [pc, #12] Get TXD = */ + 0x54, 0x21, /* movs r1, 'T' */ + 0x11, 0x60, /* str r1, [r2] */ + 0xfe, 0xe7, /* b . */ + 0x00, 0x25, 0x00, 0x40, /* 0x40002500 =3D UART ENABLE = */ + 0x08, 0x20, 0x00, 0x40, /* 0x40002008 =3D UART STARTTX= */ + 0x1c, 0x25, 0x00, 0x40 /* 0x4000251c =3D UART TXD */ +}; + typedef struct testdef { const char *arch; /* Target architecture */ const char *machine; /* Name of the machine */ @@ -105,6 +123,7 @@ static testdef_t tests[] =3D { { "hppa", "hppa", "", "SeaBIOS wants SYSTEM HALT" }, { "aarch64", "virt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64), kernel_aarch64 }, + { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 }, =20 { NULL } }; --=20 2.17.1