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X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 1/5] target/arm: Install ARMISARegisters from kvm host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ID registers are replacing (some of) the feature bits. We need (some of) these values to determine the set of data to be handled during migration. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/kvm_arm.h | 1 + target/arm/kvm.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 21c0129da2..6393455b1d 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -183,6 +183,7 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); * by asking the host kernel) */ typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; uint64_t features; uint32_t target; const char *dtb_compatible; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 09a86e2820..44dd0ce6ce 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -158,6 +158,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) =20 cpu->kvm_target =3D arm_host_cpu_features.target; cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; + cpu->isar =3D arm_host_cpu_features.isar; env->features =3D arm_host_cpu_features.features; } =20 --=20 2.17.2 From nobody Thu Nov 6 08:23:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540381456995287.54447148925715; Wed, 24 Oct 2018 04:44:16 -0700 (PDT) Received: from localhost ([::1]:47696 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFHa1-0001KE-5L for importer@patchew.org; Wed, 24 Oct 2018 07:44:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47117) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFHTk-0003AN-Mh for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFHTg-0005FD-ED for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:36 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:40692) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gFHTb-0005Bp-2Z for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:31 -0400 Received: by mail-wr1-x442.google.com with SMTP id d2-v6so5204910wro.7 for ; Wed, 24 Oct 2018 04:37:21 -0700 (PDT) Received: from cloudburst.twiddle.net.net ([185.7.230.213]) by smtp.gmail.com with ESMTPSA id c8-v6sm6769172wrb.6.2018.10.24.04.37.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Oct 2018 04:37:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mhSijd16+NJw96dqXKla0uCq/J2KTUK4WGHUbEgJAIY=; b=OQ21Bf9L4TWutpjazCf/Tv9JzuKyw+5hGsFTh9NKXvhdtvVc3SkZtIDdMEPqXbWNTG oEoem/4XEmGrOA3HyScyyGk8ynLwixSRzudkXTn6n8//AIb9E8KDdQGQCNTuqYVJFJfU VHunWUZMCBglCRGkDPXPIOeZP8ChVTIbEnvU0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mhSijd16+NJw96dqXKla0uCq/J2KTUK4WGHUbEgJAIY=; b=UwUrBU67SOFc8r9rYFEiPfSNw0UCaIKTVopZLA3pshMdbtrTlNjKRqs3t11laS1Y4V HV05UrKP5pngH3ui1P8R0wKsZsyvT1bM2RqjpUvuMVuqnxvAhQCGS8iLlLbtxDkABaK2 IX86Vt8JqL7laLYap8ZVbS4CreaoHALIQxelUcojlP6z7QBFg6cIzMu28Tu3oV+DfWLc uv5mvyibmQ8Ehu7qlWr13/bno/2hGSejmjtI4x5fKbKzPMSdnkZYQyAvOTx35I7qKS9X le8Ey94FeROUGdD8JnQXeeBhkGaiet+pVpUdp45F9G1sBYDsxq+6TfImfJRE6EJSCcmj gRlA== X-Gm-Message-State: AGRZ1gJOAuEqd0aBNSi+qar2Qwoh/EgYzwFaphApNatKlropQfDQM+SK UIX6b+RXQPZhFbcauwI0nhC50rSBBk0= X-Google-Smtp-Source: AJdET5c7UDoyAxU3Ye7PFK4t2Uhrb0PNdPPRghG3+MsE6zP4Tgz4xcsgus7x30Tyk+KHhz1N/FbPCQ== X-Received: by 2002:a5d:5342:: with SMTP id t2-v6mr2415918wrv.257.1540381040564; Wed, 24 Oct 2018 04:37:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 12:37:06 +0100 Message-Id: <20181024113709.16599-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181024113709.16599-1-richard.henderson@linaro.org> References: <20181024113709.16599-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 2/5] target/arm: Fill in ARMISARegisters for kvm64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 63 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 61 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5de8ff0ac5..6ed80eadc2 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -443,17 +443,41 @@ static inline void unset_feature(uint64_t *features, = int feature) *features &=3D ~(1ULL << feature); } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + uint64_t ret; + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)&ret }; + int err; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + err =3D ioctl(fd, KVM_GET_ONE_REG, &idreg); + if (err < 0) { + return -1; + } + assert(ret <=3D UINT32_MAX); + *pret =3D ret; + return 0; +} + +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. - * For AArch64 we currently don't care about ID registers at - * all; we just want to know the CPU type. */ int fdarray[3]; uint64_t features =3D 0; + int err =3D 0; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. Fortunately these old kernels @@ -474,8 +498,43 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) ahcf->target =3D init.target; ahcf->dtb_compatible =3D "arm,arm-v8"; =20 + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM64_SYS_REG(3, 0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM64_SYS_REG(3, 0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM64_SYS_REG(3, 0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM64_SYS_REG(3, 0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM64_SYS_REG(3, 0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM64_SYS_REG(3, 0, 0, 2, 7)); + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + ARM64_SYS_REG(3, 0, 0, 3, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + ARM64_SYS_REG(3, 0, 0, 3, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + ARM64_SYS_REG(3, 0, 0, 3, 2)); + + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, + ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, + ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, + ARM64_SYS_REG(3, 0, 0, 4, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, + ARM64_SYS_REG(3, 0, 0, 4, 1)); + kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 + if (err < 0) { + return false; + } + /* We can assume any KVM supporting CPU is at least a v8 * with VFPv4+Neon; this in turn implies most of the other * feature bits. --=20 2.17.2 From nobody Thu Nov 6 08:23:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Wed, 24 Oct 2018 04:37:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 12:37:07 +0100 Message-Id: <20181024113709.16599-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181024113709.16599-1-richard.henderson@linaro.org> References: <20181024113709.16599-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 3/5] target/arm: Introduce read_sys_reg32 for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Assert that the value to be written is the correct size. No change in functionality here, just mirroring the same function from kvm64. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/kvm32.c | 41 ++++++++++++++++------------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 0f1e94c7b5..da08f7aab8 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -28,6 +28,14 @@ static inline void set_feature(uint64_t *features, int f= eature) *features |=3D 1ULL << feature; } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U32); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -35,9 +43,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. */ - int i, ret, fdarray[3]; + int i, err =3D 0, fdarray[3]; uint32_t midr, id_pfr0, mvfr1; uint64_t features =3D 0; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. @@ -47,23 +56,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) QEMU_KVM_ARM_TARGET_NONE }; struct kvm_vcpu_init init; - struct kvm_one_reg idregs[] =3D { - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0), - .addr =3D (uintptr_t)&midr, - }, - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0), - .addr =3D (uintptr_t)&id_pfr0, - }, - { - .id =3D KVM_REG_ARM | KVM_REG_SIZE_U32 - | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1, - .addr =3D (uintptr_t)&mvfr1, - }, - }; =20 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { return false; @@ -77,16 +69,15 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) */ ahcf->dtb_compatible =3D "arm,arm-v7"; =20 - for (i =3D 0; i < ARRAY_SIZE(idregs); i++) { - ret =3D ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]); - if (ret) { - break; - } - } + err |=3D read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); + err |=3D read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, = 0)); + err |=3D read_sys_reg32(fdarray[2], &mvfr1, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 - if (ret) { + if (err < 0) { return false; } =20 --=20 2.17.2 From nobody Thu Nov 6 08:23:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 24 Oct 2018 04:37:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 12:37:08 +0100 Message-Id: <20181024113709.16599-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181024113709.16599-1-richard.henderson@linaro.org> References: <20181024113709.16599-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 4/5] target/arm: Fill in ARMISARegisters for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/kvm32.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index da08f7aab8..f23cc77d9e 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -44,7 +44,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ah= cf) * and then query that CPU for the relevant ID registers. */ int i, err =3D 0, fdarray[3]; - uint32_t midr, id_pfr0, mvfr1; + uint32_t midr, id_pfr0; uint64_t features =3D 0; =20 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -71,9 +71,32 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *a= hcf) =20 err |=3D read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); err |=3D read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, = 0)); - err |=3D read_sys_reg32(fdarray[2], &mvfr1, + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM_CP15_REG32(0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM_CP15_REG32(0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM_CP15_REG32(0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM_CP15_REG32(0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM_CP15_REG32(0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM_CP15_REG32(0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM_CP15_REG32(0, 0, 2, 7)); + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); + /* + * FIXME: There is not yet a way to read MVFR2. + * Fortunately there is not yet anything in there that affects migrati= on. + */ =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 @@ -95,13 +118,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) if (extract32(id_pfr0, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_THUMB2EE); } - if (extract32(mvfr1, 20, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 20, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } - if (extract32(mvfr1, 12, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(mvfr1, 28, 4) =3D=3D 1) { + if (extract32(ahcf->isar.mvfr1, 28, 4) =3D=3D 1) { /* FMAC support implies VFPv4 */ set_feature(&features, ARM_FEATURE_VFP4); } --=20 2.17.2 From nobody Thu Nov 6 08:23:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540381521728182.95042195766302; Wed, 24 Oct 2018 04:45:21 -0700 (PDT) Received: from localhost ([::1]:47700 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFHbC-0002Pn-Jt for importer@patchew.org; Wed, 24 Oct 2018 07:45:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFHTm-0003HY-F2 for qemu-devel@nongnu.org; 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 5/5] target/arm: Convert t32ee from feature bit to isar3 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 6 +++++- linux-user/elfload.c | 2 +- target/arm/cpu.c | 4 ---- target/arm/helper.c | 2 +- target/arm/kvm32.c | 3 --- target/arm/machine.c | 3 +-- 6 files changed, 8 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8e6779936e..895f9909d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1575,7 +1575,6 @@ enum arm_features { ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE, ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ ARM_FEATURE_V4T, @@ -3172,6 +3171,11 @@ static inline bool isar_feature_jazelle(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; } =20 +static inline bool isar_feature_t32ee(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar3, ID_ISAR3, T32EE) !=3D 0; +} + static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) !=3D 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 055f6a95ab..45d6836bb9 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -466,7 +466,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); - GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + GET_FEATURE_ID(t32ee, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8f16e96b6c..e08a2d2d79 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1440,7 +1440,6 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr =3D 0x410fc080; @@ -1509,7 +1508,6 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different @@ -1572,7 +1570,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); @@ -1618,7 +1615,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ea95b0815..bea4d5350d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5455,7 +5455,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + if (cpu_isar_feature(t32ee, cpu)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f23cc77d9e..bf39937a08 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -115,9 +115,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) set_feature(&features, ARM_FEATURE_VFP3); set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 - if (extract32(id_pfr0, 12, 4) =3D=3D 1) { - set_feature(&features, ARM_FEATURE_THUMB2EE); - } if (extract32(ahcf->isar.mvfr1, 20, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } diff --git a/target/arm/machine.c b/target/arm/machine.c index 239fe4e84d..07f904709a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -321,9 +321,8 @@ static const VMStateDescription vmstate_m =3D { static bool thumb2ee_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_THUMB2EE); + return cpu_isar_feature(t32ee, cpu); } =20 static const VMStateDescription vmstate_thumb2ee =3D { --=20 2.17.2