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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jCVrU2Px3p+CecDinWUbmAmwOcg2g2UpeV0sFGXPvGY=; b=fjrr2OnVL8fCPwQ57Hr1KQJoyK/zm9kMYQakrW5sW6KANTycYkPMQyybXnzrEk7Aj/ BeeCivA3HAUJT3f8InGsjcYOoiVWmS1LEdcTQfmzRapjUe8fCNswlH5ZN/NzC4YHm+AQ 5rJXnS/6Cnob4PKv/L+caSoPmb0DIPdlUwB5U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jCVrU2Px3p+CecDinWUbmAmwOcg2g2UpeV0sFGXPvGY=; b=DiPZMmxMe4pp8c7aSE7fC4fb8wN/A8zb7jQmo3bUBCless3dIg77snRu1un41p26+V /tWfTXkEE0FaNZYxHWLj9JDnQotCNvfGZMYrDYuMXZroea4TmFh4Dqx69QXqbMQZp8lq YsJZNI1VS/9smw8ANXJjZM6u+ZPAJyqvauQQ9iBMrtg8IKkyM4HJK9k91miUmIW8R1Lv pU5CgNucy0ZGeZ+XiJKlULUwD+/6pgB5w4FzcL/1RJ5lrR2pwVkAo3q2sGqZJjVJdOkE pSk/q+7EJuVBfkxyPGehczNyoOydxIoaJ343S9XdTQmvyk3zBzthLJVTkekkMMaoZ2tY U7QQ== X-Gm-Message-State: AGRZ1gJqQ1xXPHepDRSlBcMOQYcbNzbUUaW20OfuBEAnSCHrDu/H9VGj w2+Q5/ZYXUPUlO6IKqLJLhXs+VYmoZs= X-Google-Smtp-Source: AJdET5fqXVPLXBo6ZSiIPd9y2ctiiXfb/g3R572reRvrnW+U1em3rAzojdexHyHp82VLlcDAqYsWoQ== X-Received: by 2002:adf:fa04:: with SMTP id m4-v6mr1107363wrr.155.1540278188402; Tue, 23 Oct 2018 00:03:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:50 +0100 Message-Id: <20181023070253.6407-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 07/10] cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The difference between the two sets of APIs is now miniscule. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 58 ++++++++++------------------------------------ 1 file changed, 12 insertions(+), 46 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6b0f93ec01..4447a5f028 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -256,38 +256,6 @@ static void tlb_flush_page_locked(CPUArchState *env, i= nt midx, } } =20 -static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data) -{ - CPUArchState *env =3D cpu->env_ptr; - target_ulong addr =3D (target_ulong) data.target_ptr; - int mmu_idx; - - assert_cpu_is_self(cpu); - - tlb_debug("page addr:" TARGET_FMT_lx "\n", addr); - - addr &=3D TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_c.lock); - for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_page_locked(env, mmu_idx, addr); - } - qemu_spin_unlock(&env->tlb_c.lock); - - tb_flush_jmp_cache(cpu, addr); -} - -void tlb_flush_page(CPUState *cpu, target_ulong addr) -{ - tlb_debug("page :" TARGET_FMT_lx "\n", addr); - - if (!qemu_cpu_is_self(cpu)) { - async_run_on_cpu(cpu, tlb_flush_page_async_work, - RUN_ON_CPU_TARGET_PTR(addr)); - } else { - tlb_flush_page_async_work(cpu, RUN_ON_CPU_TARGET_PTR(addr)); - } -} - /* As we are going to hijack the bottom bits of the page address for a * mmuidx bit mask we need to fail to build if we can't do that */ @@ -337,6 +305,11 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ul= ong addr, uint16_t idxmap) } } =20 +void tlb_flush_page(CPUState *cpu, target_ulong addr) +{ + tlb_flush_page_by_mmuidx(cpu, addr, ALL_MMUIDX_BITS); +} + void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong add= r, uint16_t idxmap) { @@ -353,6 +326,11 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_c= pu, target_ulong addr, fn(src_cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); } =20 +void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) +{ + tlb_flush_page_by_mmuidx_all_cpus(src, addr, ALL_MMUIDX_BITS); +} + void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu, target_ulong addr, uint16_t idxmap) @@ -370,21 +348,9 @@ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState= *src_cpu, async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_= idx)); } =20 -void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) +void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr) { - const run_on_cpu_func fn =3D tlb_flush_page_async_work; - - flush_all_helper(src, fn, RUN_ON_CPU_TARGET_PTR(addr)); - fn(src, RUN_ON_CPU_TARGET_PTR(addr)); -} - -void tlb_flush_page_all_cpus_synced(CPUState *src, - target_ulong addr) -{ - const run_on_cpu_func fn =3D tlb_flush_page_async_work; - - flush_all_helper(src, fn, RUN_ON_CPU_TARGET_PTR(addr)); - async_safe_run_on_cpu(src, fn, RUN_ON_CPU_TARGET_PTR(addr)); + tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } =20 /* update the TLBs so that writes to code in the virtual page 'addr' --=20 2.17.2