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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.02.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:02:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9v94UO8qNEVoiiL/c5LK6+DcXBcDdMoZQJrfDDJ1Ios=; b=FjsjEnmxO75cJ09cASA9eZSUI/Q5x7aAozL6yuDV7HsDFdwUxdBPdwvVedJ45LjVX/ RkFPfkxg/oLpWJHq/ti+/etPVzm/Bf/X7nWdH5pVql3JJ6kVmHF/hdoVdQeD+IVVpRxE 2Q9LyqJBS38kSh0Uz4mMWnznj8hMzOZpS7PSM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9v94UO8qNEVoiiL/c5LK6+DcXBcDdMoZQJrfDDJ1Ios=; b=dK8uty42Dd22nifAHN6+qFufcy3qGEZ5OuEzuL1NIS7LueFi6KVnO/ueA2uit48F26 b95AL3KVVr6yxHTBqqrqYifcBkz4GtO62Zr79fQRjfKO3glJ9vVMqI3AMtAO42NC30kW cSKg03N0g0tyajXsYb5E45JoXu9M9RXXiw99/HNSl7QEhptKgwK/mEZNMkz39nRCJCw7 P+Cbzlzm+sGFGAkypTyo4FR/C8fp3AphvVPP3EJs/zNWeNn5XRCkwF9xYL29Q1ChJz9u 7WkjgCxDwt4DUWZSpEQ67P4ua9bOkfdZBJmzb+lqWLS4+eBfQ88nOcwCYwmDXDSWe8yu YDrA== X-Gm-Message-State: ABuFfohjnkXPxx42l60Y5QmDbDAM1FG4IWxZpV28WCaeNKszhm07oslc h2sBfd2LaEs9jPRTCpMbbNcRv6TbFqE= X-Google-Smtp-Source: AJdET5cpDrcCVNqRkvAe4MB/+X9cwXNjc+O31L2X0p7gxfK0T1JpiZzrJW5hxd4h648NFj3SSf6hZw== X-Received: by 2002:a1c:4054:: with SMTP id n81-v6mr19131133wma.82.1540278178520; Tue, 23 Oct 2018 00:02:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:43 +0100 Message-Id: <20181023070253.6407-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 01/10] cputlb: Move tlb_lock to CPUTLBCommon X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is the first of several moves to reduce the size of the CPU_COMMON_TLB macro and improve some locality of refernce. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-defs.h | 17 ++++++++++++--- accel/tcg/cputlb.c | 48 ++++++++++++++++++++--------------------- 2 files changed, 38 insertions(+), 27 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 4ff62f32bf..9005923b4d 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -141,10 +141,21 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; =20 +/* + * Data elements that are shared between all MMU modes. + */ +typedef struct CPUTLBCommon { + /* lock serializes updates to tlb_table and tlb_v_table */ + QemuSpin lock; +} CPUTLBCommon; + +/* + * The meaning of each of the MMU modes is defined in the target code. + * Note that NB_MMU_MODES is not yet defined; we can only reference it + * within preprocessor defines that will be expanded later. + */ #define CPU_COMMON_TLB \ - /* The meaning of the MMU modes is defined in the target code. */ \ - /* tlb_lock serializes updates to tlb_table and tlb_v_table */ \ - QemuSpin tlb_lock; \ + CPUTLBCommon tlb_c; \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index af57aca5e4..d4e07056be 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -78,7 +78,7 @@ void tlb_init(CPUState *cpu) { CPUArchState *env =3D cpu->env_ptr; =20 - qemu_spin_init(&env->tlb_lock); + qemu_spin_init(&env->tlb_c.lock); } =20 /* flush_all_helper: run fn across all cpus @@ -134,15 +134,15 @@ static void tlb_flush_nocheck(CPUState *cpu) tlb_debug("(count: %zu)\n", tlb_flush_count()); =20 /* - * tlb_table/tlb_v_table updates from any thread must hold tlb_lock. + * tlb_table/tlb_v_table updates from any thread must hold tlb_c.lock. * However, updates from the owner thread (as is the case here; see the * above assert_cpu_is_self) do not need atomic_set because all reads * that do not hold the lock are performed by the same owner thread. */ - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 @@ -195,7 +195,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) =20 tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask); =20 - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { =20 if (test_bit(mmu_idx, &mmu_idx_bitmask)) { @@ -205,7 +205,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[= 0])); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 @@ -262,7 +262,7 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tl= b_entry, tlb_hit_page(tlb_entry->addr_code, page); } =20 -/* Called with tlb_lock held */ +/* Called with tlb_c.lock held */ static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, target_ulong page) { @@ -271,7 +271,7 @@ static inline void tlb_flush_entry_locked(CPUTLBEntry *= tlb_entry, } } =20 -/* Called with tlb_lock held */ +/* Called with tlb_c.lock held */ static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_i= dx, target_ulong page) { @@ -304,12 +304,12 @@ static void tlb_flush_page_async_work(CPUState *cpu, = run_on_cpu_data data) } =20 addr &=3D TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); =20 tb_flush_jmp_cache(cpu, addr); } @@ -345,14 +345,14 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSt= ate *cpu, tlb_debug("flush page addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n", addr, mmu_idx_bitmap); =20 - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); =20 tb_flush_jmp_cache(cpu, addr); } @@ -479,7 +479,7 @@ void tlb_unprotect_code(ram_addr_t ram_addr) * te->addr_write with atomic_set. We don't need to worry about this for * oversized guests as MTTCG is disabled for them. * - * Called with tlb_lock held. + * Called with tlb_c.lock held. */ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, uintptr_t start, uintptr_t length) @@ -501,7 +501,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *t= lb_entry, } =20 /* - * Called with tlb_lock held. + * Called with tlb_c.lock held. * Called only from the vCPU context, i.e. the TLB's owner thread. */ static inline void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntr= y *s) @@ -511,7 +511,7 @@ static inline void copy_tlb_helper_locked(CPUTLBEntry *= d, const CPUTLBEntry *s) =20 /* This is a cross vCPU call (i.e. another vCPU resetting the flags of * the target vCPU). - * We must take tlb_lock to avoid racing with another vCPU update. The only + * We must take tlb_c.lock to avoid racing with another vCPU update. The o= nly * thing actually updated is the target TLB entry ->addr_write flags. */ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) @@ -521,7 +521,7 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, = ram_addr_t length) int mmu_idx; =20 env =3D cpu->env_ptr; - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; =20 @@ -535,10 +535,10 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1= , ram_addr_t length) length); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); } =20 -/* Called with tlb_lock held */ +/* Called with tlb_c.lock held */ static inline void tlb_set_dirty1_locked(CPUTLBEntry *tlb_entry, target_ulong vaddr) { @@ -557,7 +557,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) assert_cpu_is_self(cpu); =20 vaddr &=3D TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr); } @@ -568,7 +568,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); } =20 /* Our TLB does not support large pages, so remember the area covered by @@ -669,7 +669,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, * a longer critical section, but this is not a concern since the TLB = lock * is unlikely to be contended. */ - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); =20 /* Make sure there's no cached translation for the new page. */ tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); @@ -736,7 +736,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, } =20 copy_tlb_helper_locked(te, &tn); - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); } =20 /* Add a new TLB entry, but without specifying the memory @@ -917,11 +917,11 @@ static bool victim_tlb_hit(CPUArchState *env, size_t = mmu_idx, size_t index, /* Found entry in victim tlb, swap tlb and iotlb. */ CPUTLBEntry tmptlb, *tlb =3D &env->tlb_table[mmu_idx][index]; =20 - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); copy_tlb_helper_locked(&tmptlb, tlb); copy_tlb_helper_locked(tlb, vtlb); copy_tlb_helper_locked(vtlb, &tmptlb); - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); =20 CPUIOTLBEntry tmpio, *io =3D &env->iotlb[mmu_idx][index]; CPUIOTLBEntry *vio =3D &env->iotlb_v[mmu_idx][vidx]; --=20 2.17.2 From nobody Thu Nov 6 08:24:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540278562372347.4569603815572; Tue, 23 Oct 2018 00:09:22 -0700 (PDT) Received: from localhost ([::1]:38473 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqoQ-0002Iv-P0 for importer@patchew.org; Tue, 23 Oct 2018 03:09:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59582) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqm4-0008OX-8W for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEqie-0003uN-9R for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:17 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:36609) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEqid-0003k7-T3 for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:12 -0400 Received: by mail-wm1-x343.google.com with SMTP id a8-v6so547621wmf.1 for ; Tue, 23 Oct 2018 00:03:02 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (host86-153-40-62.range86-153.btcentralplus.com. [86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.02.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JG7Osc2OOobhtx/Fv9qTLXYiyheVjnvDATRHzQrsPmE=; b=c3hf+cbIKK2vujfbilhvSPmv7EwPD4BA+VbUp1QMGIB1/WY1ANY4WwB2szvyNMIKzu ZA+W08+jCPJG4fhixjrQmFnv/oGK0Rj031jahvCq+vpHnrlXmm5lIc4kON+vzfGMWFpp KCqRbmXXit4zse7QBX4RU6kr9nsCKnUZatLLc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JG7Osc2OOobhtx/Fv9qTLXYiyheVjnvDATRHzQrsPmE=; b=pjvNlxt6KXGzvCFiGJTpAl8cTaZchvQ2s+cEV9xfFtYpkZfS8CyDrj0TnJINQZNMPG AvBtX6cL6yqDKnp0lA6kjrxWLLX9XuOGP8WngPJgIqVbWDp8SkkRmz5MMkP4ux899InB fxv6uVn8uN79sBRhBVXBdFjS494wSBvdrGKNUiXKJhFAlVYvBYGxJFBedTazTlQjH2GW Lp1+KEb1JODqcSWtfwzQbA7ox9H5Dj0GTVAra+Gx0g6IX/qnc1orz3Rcuhl8jswI5WmU tu9wICD9NFA7UrVedTYU72YqWKSf2FqW2cn+aM1nxFnaaEDjOlTEb5wOpemG5fvJMqV3 AuZA== X-Gm-Message-State: ABuFfojiiRDijMmNrzcuuQYBbZRaJmihY31c8rEG1u3cKg4q6kbimMG1 8ExMfoTR/Tmx91naCeO0PMzUg8VJbjk= X-Google-Smtp-Source: ACcGV60pOPZ53qbSn6ha45bwLa4NhxrKDKKlkwwFZ4hv6UAxPvjoylWM8VnA455D2JspNcSnzMuo4Q== X-Received: by 2002:a1c:6504:: with SMTP id z4-v6mr18054796wmb.130.1540278181375; Tue, 23 Oct 2018 00:03:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:45 +0100 Message-Id: <20181023070253.6407-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 02/10] cputlb: Remove tcg_enabled hack from tlb_flush_nocheck X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The bugs this was working around were fixed with commits 022d6378c7fd target/unicore32: remove tlb_flush from uc32_init_fn 6e11beecfde0 target/alpha: remove tlb_flush from alpha_cpu_initfn Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d4e07056be..d080769c83 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -122,13 +122,6 @@ static void tlb_flush_nocheck(CPUState *cpu) { CPUArchState *env =3D cpu->env_ptr; =20 - /* The QOM tests will trigger tlb_flushes without setting up TCG - * so we bug out here in that case. - */ - if (!tcg_enabled()) { - return; - } - assert_cpu_is_self(cpu); atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); tlb_debug("(count: %zu)\n", tlb_flush_count()); --=20 2.17.2 From nobody Thu Nov 6 08:24:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540278562955660.5044051764577; Tue, 23 Oct 2018 00:09:22 -0700 (PDT) Received: from localhost ([::1]:38475 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqoR-0002KK-Vt for importer@patchew.org; Tue, 23 Oct 2018 03:09:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqm3-0008Ro-Kl for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEqid-0003tD-S9 for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:17 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:51615) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEqid-0003kv-EJ for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:11 -0400 Received: by mail-wm1-x341.google.com with SMTP id 143-v6so529641wmf.1 for ; Tue, 23 Oct 2018 00:03:03 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (host86-153-40-62.range86-153.btcentralplus.com. [86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QdTT+aLrclDVCRWmE+2W7664wr38LJMnccto55aX5rU=; b=C+L3V7zyozzMFDWJc+WI5FRj7HtMHHcz8Mtg56XUKHiGYVoo8f/d40jr1zIAn/B+nw f4+LRieEWfZV90BJfgbRUbvhYLNDX15SeNYcruW/o2O+FoLIcMNBB6cKmLtjKEsP9Sja C8yR89z3QoSPRT1Czv6e/xOlsngh5hjMPYzlg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QdTT+aLrclDVCRWmE+2W7664wr38LJMnccto55aX5rU=; b=ZB2pgXQxSTVE1vmls2pNvkP2UOACoD/NiZK0hqpnjxoOX61NkpYS4Zj2E/lkZII2HF TyId3iPkDMq1xSa6PwHSyMeJGuCrupuub+LHNOPg5CkjTHuttZTwy6Tjv9geGWiCVdZd Ydia3m3DRlzcptTmmy18gYMXX0QMIsZ+oNZEd8yvjrJOuTCRGhTun5mkHV/tXa0UfXUx 0oP32AQrw/YXdEBcICH2xybz860hHeErm3DDtasMPHUXchXrwZfhsTXwe1eCtOq4q12y qIR8uLwPgTKZO6j+CFc6lltHzlA/B2fij9YE8wg3vb2n2M1tj7PvuikT95gyBD0Eafa9 eX8g== X-Gm-Message-State: ABuFfohdnx/5sx5duFlnx+GIQkSNBdHczxr9WZE/kgFuXP+hOVkdt4tr 9iEptGFFJkiuiDyNNqogmMl8j43VbcY= X-Google-Smtp-Source: AJdET5eKa52WgO8Q+ZniIXxBkQ8bO2kbD2x+sWYmLBcQ8EXaNY+uVDFYcoYubTgoCCgd3J9e+dLjqg== X-Received: by 2002:a1c:8bcc:: with SMTP id n195-v6mr20008600wmd.118.1540278182725; Tue, 23 Oct 2018 00:03:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:46 +0100 Message-Id: <20181023070253.6407-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 03/10] cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flush X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Protect it with the tlb_lock instead of using atomics. The move puts it in or near the same cacheline as the lock; using the lock means we don't need a second atomic operation in order to perform the update. Which makes it cheap to also update pending_flush in tlb_flush_by_mmuidx_async_work. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 8 +++++++- include/qom/cpu.h | 6 ------ accel/tcg/cputlb.c | 35 +++++++++++++++++++++++------------ 3 files changed, 30 insertions(+), 19 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 9005923b4d..659c73d2a1 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -145,8 +145,14 @@ typedef struct CPUIOTLBEntry { * Data elements that are shared between all MMU modes. */ typedef struct CPUTLBCommon { - /* lock serializes updates to tlb_table and tlb_v_table */ + /* Serialize updates to tlb_table and tlb_v_table, and others as noted= . */ QemuSpin lock; + /* + * Within pending_flush, for each bit N, there exists an outstanding + * cross-cpu flush for mmu_idx N. Further cross-cpu flushes to that + * mmu_idx may be discarded. Protected by tlb_c.lock. + */ + uint16_t pending_flush; } CPUTLBCommon; =20 /* diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 4e238b0d9f..c0d13064c9 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -429,12 +429,6 @@ struct CPUState { =20 struct hax_vcpu_state *hax_vcpu; =20 - /* The pending_tlb_flush flag is set and cleared atomically to - * avoid potential races. The aim of the flag is to avoid - * unnecessary flushes. - */ - uint16_t pending_tlb_flush; - int hvf_fd; =20 /* track IOMMUs whose translations we've cached in the TCG TLB */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d080769c83..abcd08a8a2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -133,6 +133,7 @@ static void tlb_flush_nocheck(CPUState *cpu) * that do not hold the lock are performed by the same owner thread. */ qemu_spin_lock(&env->tlb_c.lock); + env->tlb_c.pending_flush =3D 0; memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); qemu_spin_unlock(&env->tlb_c.lock); @@ -142,8 +143,6 @@ static void tlb_flush_nocheck(CPUState *cpu) env->vtlb_index =3D 0; env->tlb_flush_addr =3D -1; env->tlb_flush_mask =3D 0; - - atomic_mb_set(&cpu->pending_tlb_flush, 0); } =20 static void tlb_flush_global_async_work(CPUState *cpu, run_on_cpu_data dat= a) @@ -154,8 +153,15 @@ static void tlb_flush_global_async_work(CPUState *cpu,= run_on_cpu_data data) void tlb_flush(CPUState *cpu) { if (cpu->created && !qemu_cpu_is_self(cpu)) { - if (atomic_mb_read(&cpu->pending_tlb_flush) !=3D ALL_MMUIDX_BITS) { - atomic_mb_set(&cpu->pending_tlb_flush, ALL_MMUIDX_BITS); + CPUArchState *env =3D cpu->env_ptr; + uint16_t pending; + + qemu_spin_lock(&env->tlb_c.lock); + pending =3D env->tlb_c.pending_flush; + env->tlb_c.pending_flush =3D ALL_MMUIDX_BITS; + qemu_spin_unlock(&env->tlb_c.lock); + + if (pending !=3D ALL_MMUIDX_BITS) { async_run_on_cpu(cpu, tlb_flush_global_async_work, RUN_ON_CPU_NULL); } @@ -189,6 +195,8 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask); =20 qemu_spin_lock(&env->tlb_c.lock); + env->tlb_c.pending_flush &=3D ~mmu_idx_bitmask; + for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { =20 if (test_bit(mmu_idx, &mmu_idx_bitmask)) { @@ -210,19 +218,22 @@ void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxm= ap) tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap); =20 if (!qemu_cpu_is_self(cpu)) { - uint16_t pending_flushes =3D idxmap; - pending_flushes &=3D ~atomic_mb_read(&cpu->pending_tlb_flush); + CPUArchState *env =3D cpu->env_ptr; + uint16_t pending, to_clean; =20 - if (pending_flushes) { - tlb_debug("reduced mmu_idx: 0x%" PRIx16 "\n", pending_flushes); + qemu_spin_lock(&env->tlb_c.lock); + pending =3D env->tlb_c.pending_flush; + to_clean =3D idxmap & ~pending; + env->tlb_c.pending_flush =3D pending | idxmap; + qemu_spin_unlock(&env->tlb_c.lock); =20 - atomic_or(&cpu->pending_tlb_flush, pending_flushes); + if (to_clean) { + tlb_debug("reduced mmu_idx: 0x%" PRIx16 "\n", to_clean); async_run_on_cpu(cpu, tlb_flush_by_mmuidx_async_work, - RUN_ON_CPU_HOST_INT(pending_flushes)); + RUN_ON_CPU_HOST_INT(to_clean)); } } else { - tlb_flush_by_mmuidx_async_work(cpu, - RUN_ON_CPU_HOST_INT(idxmap)); + tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(idxmap)); } } =20 --=20 2.17.2 From nobody Thu Nov 6 08:24:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540279108245615.173422031044; Tue, 23 Oct 2018 00:18:28 -0700 (PDT) Received: from localhost ([::1]:38538 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqxP-0002U3-1N for importer@patchew.org; Tue, 23 Oct 2018 03:18:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqm3-0008Rl-OS for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEqif-0003wQ-3D for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:18 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:35621) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEqie-0003mn-AB for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:12 -0400 Received: by mail-wm1-x343.google.com with SMTP id w186-v6so551491wmf.0 for ; Tue, 23 Oct 2018 00:03:06 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (host86-153-40-62.range86-153.btcentralplus.com. [86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ei4NQbVPRIt5lqbMkVeEwvfJAULjrp+cmAiYYkxBlVk=; b=TBsGqLQdVdsaCQjhQF0038x7HRkbVUTVzvr8eb+5Y0edjMHsTJlNZyUM9azzqTNu0w ovCKdDOkOd+7SZznFmaODe2aCEKdlb1Pji4vuxfG3QvMMcKHXCIgzVS64UNWZRQ1Tkbf Kj5w5R4t46EkksdA6PbMbobo9wKy0Z5O5jJQA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ei4NQbVPRIt5lqbMkVeEwvfJAULjrp+cmAiYYkxBlVk=; b=aqlajq5xbDSyl1WhEMB6Bq4/FCFUr2t1pkjhYCDxcsBShH9TE89arviatAsW8t1EeM MLi2e1DHACIs+yQWpOjtg8dKXT0ZcqK22+vEuMKmX4fec6ZwR4nQleffZ5i00p6ahWBf CqeF2rlTRZ/imKcKtvMzc8q4n3SlrjvFq18rQNWFcf1I9QjlZF36NawmUmKKbZnEB/WD 9dBebXmSvl3cyTwQGC1UneccdIjOZrgFyB3yH8sxzAeeikKrsqs/YRsTDkXuE/dpQDiJ 3oPc5thh5P7sd1cIOmzU59nsb6rQiXYyMgdCrqD3vlT1AWwTkTlzqaYmrC7hZjz830hp Dvtg== X-Gm-Message-State: AGRZ1gIHaM0ydWluYbl/2CAlSTffTc75clYBJQpUEzj82uGPQRRjlTjF NW+vrRyf/xbyIzFeL+LQudgmTPB8R0o= X-Google-Smtp-Source: AJdET5ebrwk7llK5MiY/QvaRwbdMMFxyncbonGgx2bSgwgxjVMmuKTy/RVKkBJSSTuIgVd8JrvN4bw== X-Received: by 2002:a1c:7a0a:: with SMTP id v10-v6mr1842693wmc.41.1540278184499; Tue, 23 Oct 2018 00:03:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:47 +0100 Message-Id: <20181023070253.6407-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 04/10] cputlb: Split large page tracking per mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The set of large pages in the kernel is probably not the same as the set of large pages in the application. Forcing one range to cover both will flush more often than necessary. This allows tlb_flush_page_async_work to flush just the one mmu_idx implicated, which in turn allows us to remove tlb_check_page_and_flush_by_mmuidx_async_work. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 14 +++- accel/tcg/cputlb.c | 139 ++++++++++++++++++---------------------- 2 files changed, 74 insertions(+), 79 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 659c73d2a1..df8ae18d9d 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -141,6 +141,17 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; =20 +typedef struct CPUTLBDesc { + /* + * Describe a region covering all of the large pages allocated + * into the tlb. When any page within this region is flushed, + * we must flush the entire tlb. The region is matched if + * (addr & large_page_mask) =3D=3D large_page_addr. + */ + target_ulong large_page_addr; + target_ulong large_page_mask; +} CPUTLBDesc; + /* * Data elements that are shared between all MMU modes. */ @@ -162,13 +173,12 @@ typedef struct CPUTLBCommon { */ #define CPU_COMMON_TLB \ CPUTLBCommon tlb_c; \ + CPUTLBDesc tlb_d[NB_MMU_MODES]; \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ size_t tlb_flush_count; \ - target_ulong tlb_flush_addr; \ - target_ulong tlb_flush_mask; \ target_ulong vtlb_index; \ =20 #else diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index abcd08a8a2..72b0567f70 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -113,6 +113,14 @@ size_t tlb_flush_count(void) return count; } =20 +static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) +{ + memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0])); + memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0])); + env->tlb_d[mmu_idx].large_page_addr =3D -1; + env->tlb_d[mmu_idx].large_page_mask =3D -1; +} + /* This is OK because CPU architectures generally permit an * implementation to drop entries from the TLB at any time, so * flushing more entries than required is only an efficiency issue, @@ -121,6 +129,7 @@ size_t tlb_flush_count(void) static void tlb_flush_nocheck(CPUState *cpu) { CPUArchState *env =3D cpu->env_ptr; + int mmu_idx; =20 assert_cpu_is_self(cpu); atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); @@ -134,15 +143,14 @@ static void tlb_flush_nocheck(CPUState *cpu) */ qemu_spin_lock(&env->tlb_c.lock); env->tlb_c.pending_flush =3D 0; - memset(env->tlb_table, -1, sizeof(env->tlb_table)); - memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); + for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + tlb_flush_one_mmuidx_locked(env, mmu_idx); + } qemu_spin_unlock(&env->tlb_c.lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 env->vtlb_index =3D 0; - env->tlb_flush_addr =3D -1; - env->tlb_flush_mask =3D 0; } =20 static void tlb_flush_global_async_work(CPUState *cpu, run_on_cpu_data dat= a) @@ -192,25 +200,19 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *= cpu, run_on_cpu_data data) =20 assert_cpu_is_self(cpu); =20 - tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask); + tlb_debug("mmu_idx:0x%04lx\n", mmu_idx_bitmask); =20 qemu_spin_lock(&env->tlb_c.lock); env->tlb_c.pending_flush &=3D ~mmu_idx_bitmask; =20 for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - if (test_bit(mmu_idx, &mmu_idx_bitmask)) { - tlb_debug("%d\n", mmu_idx); - - memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0])); - memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[= 0])); + tlb_flush_one_mmuidx_locked(env, mmu_idx); } } qemu_spin_unlock(&env->tlb_c.lock); =20 cpu_tb_jmp_cache_clear(cpu); - - tlb_debug("done\n"); } =20 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) @@ -287,6 +289,25 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchS= tate *env, int mmu_idx, } } =20 +static void tlb_flush_page_locked(CPUArchState *env, int midx, + target_ulong addr) +{ + target_ulong lp_addr =3D env->tlb_d[midx].large_page_addr; + target_ulong lp_mask =3D env->tlb_d[midx].large_page_mask; + + /* Check if we need to flush due to large pages. */ + if ((addr & lp_mask) =3D=3D lp_addr) { + tlb_debug("forcing full flush midx %d (" + TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", + midx, lp_addr, lp_mask); + tlb_flush_one_mmuidx_locked(env, midx); + } else { + int pidx =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + tlb_flush_entry_locked(&env->tlb_table[midx][pidx], addr); + tlb_flush_vtlb_page_locked(env, midx, addr); + } +} + static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data) { CPUArchState *env =3D cpu->env_ptr; @@ -295,23 +316,12 @@ static void tlb_flush_page_async_work(CPUState *cpu, = run_on_cpu_data data) =20 assert_cpu_is_self(cpu); =20 - tlb_debug("page :" TARGET_FMT_lx "\n", addr); - - /* Check if we need to flush due to large pages. */ - if ((addr & env->tlb_flush_mask) =3D=3D env->tlb_flush_addr) { - tlb_debug("forcing full flush (" - TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", - env->tlb_flush_addr, env->tlb_flush_mask); - - tlb_flush(cpu); - return; - } + tlb_debug("page addr:" TARGET_FMT_lx "\n", addr); =20 addr &=3D TARGET_PAGE_MASK; qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); - tlb_flush_vtlb_page_locked(env, mmu_idx, addr); + tlb_flush_page_locked(env, mmu_idx, addr); } qemu_spin_unlock(&env->tlb_c.lock); =20 @@ -346,14 +356,13 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSt= ate *cpu, =20 assert_cpu_is_self(cpu); =20 - tlb_debug("flush page addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n", + tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n", addr, mmu_idx_bitmap); =20 qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { - tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); - tlb_flush_vtlb_page_locked(env, mmu_idx, addr); + tlb_flush_page_locked(env, mmu_idx, addr); } } qemu_spin_unlock(&env->tlb_c.lock); @@ -361,29 +370,6 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSta= te *cpu, tb_flush_jmp_cache(cpu, addr); } =20 -static void tlb_check_page_and_flush_by_mmuidx_async_work(CPUState *cpu, - run_on_cpu_data = data) -{ - CPUArchState *env =3D cpu->env_ptr; - target_ulong addr_and_mmuidx =3D (target_ulong) data.target_ptr; - target_ulong addr =3D addr_and_mmuidx & TARGET_PAGE_MASK; - unsigned long mmu_idx_bitmap =3D addr_and_mmuidx & ALL_MMUIDX_BITS; - - tlb_debug("addr:"TARGET_FMT_lx" mmu_idx: %04lx\n", addr, mmu_idx_bitma= p); - - /* Check if we need to flush due to large pages. */ - if ((addr & env->tlb_flush_mask) =3D=3D env->tlb_flush_addr) { - tlb_debug("forced full flush (" - TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", - env->tlb_flush_addr, env->tlb_flush_mask); - - tlb_flush_by_mmuidx_async_work(cpu, - RUN_ON_CPU_HOST_INT(mmu_idx_bitmap)= ); - } else { - tlb_flush_page_by_mmuidx_async_work(cpu, data); - } -} - void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t i= dxmap) { target_ulong addr_and_mmu_idx; @@ -395,10 +381,10 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_u= long addr, uint16_t idxmap) addr_and_mmu_idx |=3D idxmap; =20 if (!qemu_cpu_is_self(cpu)) { - async_run_on_cpu(cpu, tlb_check_page_and_flush_by_mmuidx_async_wor= k, + async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_work, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); } else { - tlb_check_page_and_flush_by_mmuidx_async_work( + tlb_flush_page_by_mmuidx_async_work( cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); } } @@ -406,7 +392,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulo= ng addr, uint16_t idxmap) void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong add= r, uint16_t idxmap) { - const run_on_cpu_func fn =3D tlb_check_page_and_flush_by_mmuidx_async_= work; + const run_on_cpu_func fn =3D tlb_flush_page_by_mmuidx_async_work; target_ulong addr_and_mmu_idx; =20 tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap); @@ -420,10 +406,10 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_= cpu, target_ulong addr, } =20 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu, - target_ulong a= ddr, - uint16_t idxma= p) + target_ulong addr, + uint16_t idxmap) { - const run_on_cpu_func fn =3D tlb_check_page_and_flush_by_mmuidx_async_= work; + const run_on_cpu_func fn =3D tlb_flush_page_by_mmuidx_async_work; target_ulong addr_and_mmu_idx; =20 tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap); @@ -577,25 +563,26 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) =20 /* Our TLB does not support large pages, so remember the area covered by large pages and trigger a full TLB flush if these are invalidated. */ -static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, - target_ulong size) +static void tlb_add_large_page(CPUArchState *env, int mmu_idx, + target_ulong vaddr, target_ulong size) { - target_ulong mask =3D ~(size - 1); + target_ulong lp_addr =3D env->tlb_d[mmu_idx].large_page_addr; + target_ulong lp_mask =3D ~(size - 1); =20 - if (env->tlb_flush_addr =3D=3D (target_ulong)-1) { - env->tlb_flush_addr =3D vaddr & mask; - env->tlb_flush_mask =3D mask; - return; + if (lp_addr =3D=3D (target_ulong)-1) { + /* No previous large page. */ + lp_addr =3D vaddr; + } else { + /* Extend the existing region to include the new page. + This is a compromise between unnecessary flushes and + the cost of maintaining a full variable size TLB. */ + lp_mask &=3D env->tlb_d[mmu_idx].large_page_mask; + while (((lp_addr ^ vaddr) & lp_mask) !=3D 0) { + lp_mask <<=3D 1; + } } - /* Extend the existing region to include the new page. - This is a compromise between unnecessary flushes and the cost - of maintaining a full variable size TLB. */ - mask &=3D env->tlb_flush_mask; - while (((env->tlb_flush_addr ^ vaddr) & mask) !=3D 0) { - mask <<=3D 1; - } - env->tlb_flush_addr &=3D mask; - env->tlb_flush_mask =3D mask; + env->tlb_d[mmu_idx].large_page_addr =3D lp_addr & lp_mask; + env->tlb_d[mmu_idx].large_page_mask =3D lp_mask; } =20 /* Add a new TLB entry. At most one entry for a given virtual address @@ -622,12 +609,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, =20 assert_cpu_is_self(cpu); =20 - if (size < TARGET_PAGE_SIZE) { + if (size <=3D TARGET_PAGE_SIZE) { sz =3D TARGET_PAGE_SIZE; } else { - if (size > TARGET_PAGE_SIZE) { - tlb_add_large_page(env, vaddr, size); - } + tlb_add_large_page(env, mmu_idx, vaddr, size); sz =3D size; } vaddr_page =3D vaddr & TARGET_PAGE_MASK; --=20 2.17.2 From nobody Thu Nov 6 08:24:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 154027856165491.78459515271084; Tue, 23 Oct 2018 00:09:21 -0700 (PDT) Received: from localhost ([::1]:38476 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqoU-0002MB-8c for importer@patchew.org; Tue, 23 Oct 2018 03:09:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60102) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqm3-0008RT-IS for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEqie-0003u4-7W for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:17 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:36610) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEqid-0003oD-OB for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:11 -0400 Received: by mail-wm1-x343.google.com with SMTP id a8-v6so547874wmf.1 for ; Tue, 23 Oct 2018 00:03:06 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (host86-153-40-62.range86-153.btcentralplus.com. [86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/KAHHOKz5/09uNy3szZc7ufuP1mXp9/ljoylRihFv20=; b=SbIop8mcTCRD74C0U7FihO3q0K8CreiBq2LSVGRRimB19I5ploZAWuQqQCahiPXFc2 wjypJKhDP0yHLFzMtwJMEJ3TihXFuUScA4/Z0y8jPqgdd1kNMH4aorBuOawNqQ2DQQz5 2ZlpSH8wSsM9U63k7CuB1LTpJAzPZOQqFVF6A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/KAHHOKz5/09uNy3szZc7ufuP1mXp9/ljoylRihFv20=; b=qNCWxEarv56Mq21zAS+KKQL+Itfx8mDlPvCOX9UBoFy8vZjenfMHLxecTXHi9rHb1a s4pQNHJkxxtUCSblg+HlfrLh1zfZRZJzqB83/CeqqpWGJi8uaMTdGEzmtu8jro0NVHbf U+pLb1tiRCGQotIHzYIoB8N52uMdsLm6PU3xCJFZOz4u4IvTJRiveMhLbXdJuL2Mbwdt fwSqEFsbLafPU0YZmX7egboLvGqfZ6WHypp5BK+DzqzXx4JxcS1wHuRX8uKVFAMKioci RsbnvBptETS3KrJijMKuytCblmkC1wyufSxk9lSf/Mpy5T5ncM5GfWGXpYdi+xBFdaSe SXhA== X-Gm-Message-State: ABuFfojiTxr1MvxyqW6wfC6s603Z5KdE/N7Px0eyi8pOL4qz2IFPI8Cg IO/0OQCR79gUUu1OLrUee/0BMPMNky4= X-Google-Smtp-Source: ACcGV60VFObq0ZbE/kXpMRb2BpmmSKa+pZ39glcHUxFN4UKWa/94/tqVwvws/mK5XozEDwGcqVmfyQ== X-Received: by 2002:a1c:9ca:: with SMTP id 193-v6mr19663889wmj.86.1540278185608; Tue, 23 Oct 2018 00:03:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:48 +0100 Message-Id: <20181023070253.6407-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 05/10] cputlb: Move env->vtlb_index to env->tlb_d.vindex X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The rest of the tlb victim cache is per-tlb, the next use index should be as well. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-defs.h | 5 +++-- accel/tcg/cputlb.c | 5 ++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index df8ae18d9d..181c0dbfa4 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -150,6 +150,8 @@ typedef struct CPUTLBDesc { */ target_ulong large_page_addr; target_ulong large_page_mask; + /* The next index to use in the tlb victim table. */ + size_t vindex; } CPUTLBDesc; =20 /* @@ -178,8 +180,7 @@ typedef struct CPUTLBCommon { CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ - size_t tlb_flush_count; \ - target_ulong vtlb_index; \ + size_t tlb_flush_count; =20 #else =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 72b0567f70..d3b37ffa85 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -119,6 +119,7 @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *e= nv, int mmu_idx) memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0])); env->tlb_d[mmu_idx].large_page_addr =3D -1; env->tlb_d[mmu_idx].large_page_mask =3D -1; + env->tlb_d[mmu_idx].vindex =3D 0; } =20 /* This is OK because CPU architectures generally permit an @@ -149,8 +150,6 @@ static void tlb_flush_nocheck(CPUState *cpu) qemu_spin_unlock(&env->tlb_c.lock); =20 cpu_tb_jmp_cache_clear(cpu); - - env->vtlb_index =3D 0; } =20 static void tlb_flush_global_async_work(CPUState *cpu, run_on_cpu_data dat= a) @@ -668,7 +667,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, * different page; otherwise just overwrite the stale data. */ if (!tlb_hit_page_anyprot(te, vaddr_page)) { - unsigned vidx =3D env->vtlb_index++ % CPU_VTLB_SIZE; + unsigned vidx =3D env->tlb_d[mmu_idx].vindex++ % CPU_VTLB_SIZE; CPUTLBEntry *tv =3D &env->tlb_v_table[mmu_idx][vidx]; =20 /* Evict the old entry into the victim tlb. */ --=20 2.17.2 From nobody Thu Nov 6 08:24:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540278561638362.5976286410812; Tue, 23 Oct 2018 00:09:21 -0700 (PDT) Received: from localhost ([::1]:38474 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqoS-0002K4-Cl for importer@patchew.org; Tue, 23 Oct 2018 03:09:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59895) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqm2-0008Q6-8Y for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEqie-0003uc-DZ for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:20 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:46004) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEqid-0003p6-Ub for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:12 -0400 Received: by mail-wr1-x444.google.com with SMTP id f17-v6so341983wrs.12 for ; Tue, 23 Oct 2018 00:03:08 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (host86-153-40-62.range86-153.btcentralplus.com. [86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kk1qq57GJPL/Lh6dxNjkZlKloxkDADekJnNQMyq/28E=; b=CbFaDFGHQSWoeHOG56m9DzFmBDZrL/eDFxPYJ2KDkWKclUPAMTz8OWG/51fiTVehNf +U0QfBm3EX2zNcmGQR2od4j4zCdDw/Om+ztaCcJ7QpbyA+d3Kz0dBnUnvJUNmnoYOdYM A6xih7Tb0tskFyLuIJ+jnLqzbGkHscHJKah7I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kk1qq57GJPL/Lh6dxNjkZlKloxkDADekJnNQMyq/28E=; b=M6+s520rHLLizqwU+HO3jJKS8uQcQG6hF9ydtVpEFFviDhssjAFhTyuxRw85h8gsHu eLk8Xx/XutNji0C2k2xqXtVTGzu1Vq9hYjzpJbka3ltenVlqgfgrz7W90ASbWU8YfYNs YpijcZLq44WETsPGG6AnNPd7DdeCW1euuYxFHWUX9Y9TJTkXrnJe4Rwf23tcOKjxS69U W5TOgMucfPtjFusrpLI4A+WudVcVDAuP0uGmMYWiueTDC+Kv+f6PLu0J2vuYyCd44KuG WqKOu89BQUGkL3LYXVMtjtqKkeU819eU6g6VU3FEUoKJnEbVpKypu1cJXjxvCE/isIxp dFjw== X-Gm-Message-State: AGRZ1gLpdoVs4sgK7Kw9C2XI9tzg9fUd8g0/u9qN39QnD7O/P/PCzGpw UyKgRYoevaTSi8eAcEzGUN9wd1svBzw= X-Google-Smtp-Source: AJdET5cZVCfPJtW+fsGWVqiX4PUlSZAtOXadA/43cCE2ZvqSpgqYGqDlb56az0iogBYazT2Lb8Hanw== X-Received: by 2002:a5d:67d2:: with SMTP id n18-v6mr4968255wrw.245.1540278186913; Tue, 23 Oct 2018 00:03:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:49 +0100 Message-Id: <20181023070253.6407-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 06/10] cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_work X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The difference between the two sets of APIs is now miniscule. This allows tlb_flush, tlb_flush_all_cpus, and tlb_flush_all_cpus_synced to be merged with their corresponding by_mmuidx functions as well. For accounting, consider mmu_idx_bitmask =3D ALL_MMUIDX_BITS to be a full flush. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 93 +++++++++++----------------------------------- 1 file changed, 21 insertions(+), 72 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d3b37ffa85..6b0f93ec01 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -122,75 +122,6 @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *= env, int mmu_idx) env->tlb_d[mmu_idx].vindex =3D 0; } =20 -/* This is OK because CPU architectures generally permit an - * implementation to drop entries from the TLB at any time, so - * flushing more entries than required is only an efficiency issue, - * not a correctness issue. - */ -static void tlb_flush_nocheck(CPUState *cpu) -{ - CPUArchState *env =3D cpu->env_ptr; - int mmu_idx; - - assert_cpu_is_self(cpu); - atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); - tlb_debug("(count: %zu)\n", tlb_flush_count()); - - /* - * tlb_table/tlb_v_table updates from any thread must hold tlb_c.lock. - * However, updates from the owner thread (as is the case here; see the - * above assert_cpu_is_self) do not need atomic_set because all reads - * that do not hold the lock are performed by the same owner thread. - */ - qemu_spin_lock(&env->tlb_c.lock); - env->tlb_c.pending_flush =3D 0; - for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_one_mmuidx_locked(env, mmu_idx); - } - qemu_spin_unlock(&env->tlb_c.lock); - - cpu_tb_jmp_cache_clear(cpu); -} - -static void tlb_flush_global_async_work(CPUState *cpu, run_on_cpu_data dat= a) -{ - tlb_flush_nocheck(cpu); -} - -void tlb_flush(CPUState *cpu) -{ - if (cpu->created && !qemu_cpu_is_self(cpu)) { - CPUArchState *env =3D cpu->env_ptr; - uint16_t pending; - - qemu_spin_lock(&env->tlb_c.lock); - pending =3D env->tlb_c.pending_flush; - env->tlb_c.pending_flush =3D ALL_MMUIDX_BITS; - qemu_spin_unlock(&env->tlb_c.lock); - - if (pending !=3D ALL_MMUIDX_BITS) { - async_run_on_cpu(cpu, tlb_flush_global_async_work, - RUN_ON_CPU_NULL); - } - } else { - tlb_flush_nocheck(cpu); - } -} - -void tlb_flush_all_cpus(CPUState *src_cpu) -{ - const run_on_cpu_func fn =3D tlb_flush_global_async_work; - flush_all_helper(src_cpu, fn, RUN_ON_CPU_NULL); - fn(src_cpu, RUN_ON_CPU_NULL); -} - -void tlb_flush_all_cpus_synced(CPUState *src_cpu) -{ - const run_on_cpu_func fn =3D tlb_flush_global_async_work; - flush_all_helper(src_cpu, fn, RUN_ON_CPU_NULL); - async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_NULL); -} - static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data = data) { CPUArchState *env =3D cpu->env_ptr; @@ -212,13 +143,17 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *= cpu, run_on_cpu_data data) qemu_spin_unlock(&env->tlb_c.lock); =20 cpu_tb_jmp_cache_clear(cpu); + + if (mmu_idx_bitmask =3D=3D ALL_MMUIDX_BITS) { + atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + } } =20 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) { tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap); =20 - if (!qemu_cpu_is_self(cpu)) { + if (cpu->created && !qemu_cpu_is_self(cpu)) { CPUArchState *env =3D cpu->env_ptr; uint16_t pending, to_clean; =20 @@ -238,6 +173,11 @@ void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxma= p) } } =20 +void tlb_flush(CPUState *cpu) +{ + tlb_flush_by_mmuidx(cpu, ALL_MMUIDX_BITS); +} + void tlb_flush_by_mmuidx_all_cpus(CPUState *src_cpu, uint16_t idxmap) { const run_on_cpu_func fn =3D tlb_flush_by_mmuidx_async_work; @@ -248,8 +188,12 @@ void tlb_flush_by_mmuidx_all_cpus(CPUState *src_cpu, u= int16_t idxmap) fn(src_cpu, RUN_ON_CPU_HOST_INT(idxmap)); } =20 -void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, - uint16_t idxmap) +void tlb_flush_all_cpus(CPUState *src_cpu) +{ + tlb_flush_by_mmuidx_all_cpus(src_cpu, ALL_MMUIDX_BITS); +} + +void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxma= p) { const run_on_cpu_func fn =3D tlb_flush_by_mmuidx_async_work; =20 @@ -259,6 +203,11 @@ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src= _cpu, async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap)); } =20 +void tlb_flush_all_cpus_synced(CPUState *src_cpu) +{ + tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS); +} + static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry, target_ulong page) { --=20 2.17.2 From nobody Thu Nov 6 08:24:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jCVrU2Px3p+CecDinWUbmAmwOcg2g2UpeV0sFGXPvGY=; b=fjrr2OnVL8fCPwQ57Hr1KQJoyK/zm9kMYQakrW5sW6KANTycYkPMQyybXnzrEk7Aj/ BeeCivA3HAUJT3f8InGsjcYOoiVWmS1LEdcTQfmzRapjUe8fCNswlH5ZN/NzC4YHm+AQ 5rJXnS/6Cnob4PKv/L+caSoPmb0DIPdlUwB5U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jCVrU2Px3p+CecDinWUbmAmwOcg2g2UpeV0sFGXPvGY=; b=DiPZMmxMe4pp8c7aSE7fC4fb8wN/A8zb7jQmo3bUBCless3dIg77snRu1un41p26+V /tWfTXkEE0FaNZYxHWLj9JDnQotCNvfGZMYrDYuMXZroea4TmFh4Dqx69QXqbMQZp8lq YsJZNI1VS/9smw8ANXJjZM6u+ZPAJyqvauQQ9iBMrtg8IKkyM4HJK9k91miUmIW8R1Lv pU5CgNucy0ZGeZ+XiJKlULUwD+/6pgB5w4FzcL/1RJ5lrR2pwVkAo3q2sGqZJjVJdOkE pSk/q+7EJuVBfkxyPGehczNyoOydxIoaJ343S9XdTQmvyk3zBzthLJVTkekkMMaoZ2tY U7QQ== X-Gm-Message-State: AGRZ1gJqQ1xXPHepDRSlBcMOQYcbNzbUUaW20OfuBEAnSCHrDu/H9VGj w2+Q5/ZYXUPUlO6IKqLJLhXs+VYmoZs= X-Google-Smtp-Source: AJdET5fqXVPLXBo6ZSiIPd9y2ctiiXfb/g3R572reRvrnW+U1em3rAzojdexHyHp82VLlcDAqYsWoQ== X-Received: by 2002:adf:fa04:: with SMTP id m4-v6mr1107363wrr.155.1540278188402; Tue, 23 Oct 2018 00:03:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:50 +0100 Message-Id: <20181023070253.6407-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 07/10] cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The difference between the two sets of APIs is now miniscule. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 58 ++++++++++------------------------------------ 1 file changed, 12 insertions(+), 46 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6b0f93ec01..4447a5f028 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -256,38 +256,6 @@ static void tlb_flush_page_locked(CPUArchState *env, i= nt midx, } } =20 -static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data) -{ - CPUArchState *env =3D cpu->env_ptr; - target_ulong addr =3D (target_ulong) data.target_ptr; - int mmu_idx; - - assert_cpu_is_self(cpu); - - tlb_debug("page addr:" TARGET_FMT_lx "\n", addr); - - addr &=3D TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_c.lock); - for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_page_locked(env, mmu_idx, addr); - } - qemu_spin_unlock(&env->tlb_c.lock); - - tb_flush_jmp_cache(cpu, addr); -} - -void tlb_flush_page(CPUState *cpu, target_ulong addr) -{ - tlb_debug("page :" TARGET_FMT_lx "\n", addr); - - if (!qemu_cpu_is_self(cpu)) { - async_run_on_cpu(cpu, tlb_flush_page_async_work, - RUN_ON_CPU_TARGET_PTR(addr)); - } else { - tlb_flush_page_async_work(cpu, RUN_ON_CPU_TARGET_PTR(addr)); - } -} - /* As we are going to hijack the bottom bits of the page address for a * mmuidx bit mask we need to fail to build if we can't do that */ @@ -337,6 +305,11 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ul= ong addr, uint16_t idxmap) } } =20 +void tlb_flush_page(CPUState *cpu, target_ulong addr) +{ + tlb_flush_page_by_mmuidx(cpu, addr, ALL_MMUIDX_BITS); +} + void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong add= r, uint16_t idxmap) { @@ -353,6 +326,11 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_c= pu, target_ulong addr, fn(src_cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); } =20 +void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) +{ + tlb_flush_page_by_mmuidx_all_cpus(src, addr, ALL_MMUIDX_BITS); +} + void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu, target_ulong addr, uint16_t idxmap) @@ -370,21 +348,9 @@ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState= *src_cpu, async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_= idx)); } =20 -void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) +void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr) { - const run_on_cpu_func fn =3D tlb_flush_page_async_work; - - flush_all_helper(src, fn, RUN_ON_CPU_TARGET_PTR(addr)); - fn(src, RUN_ON_CPU_TARGET_PTR(addr)); -} - -void tlb_flush_page_all_cpus_synced(CPUState *src, - target_ulong addr) -{ - const run_on_cpu_func fn =3D tlb_flush_page_async_work; - - flush_all_helper(src, fn, RUN_ON_CPU_TARGET_PTR(addr)); - async_safe_run_on_cpu(src, fn, RUN_ON_CPU_TARGET_PTR(addr)); + tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } =20 /* update the TLBs so that writes to code in the virtual page 'addr' --=20 2.17.2 From nobody Thu Nov 6 08:24:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540278727372579.9768281927026; Tue, 23 Oct 2018 00:12:07 -0700 (PDT) Received: from localhost ([::1]:38494 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqrF-0004eG-LQ for importer@patchew.org; Tue, 23 Oct 2018 03:12:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqm4-0008O1-Vz for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEqif-0003wI-39 for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:17 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:41410) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEqie-0003rh-CZ for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:12 -0400 Received: by mail-wr1-x443.google.com with SMTP id q7-v6so356515wrr.8 for ; Tue, 23 Oct 2018 00:03:11 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (host86-153-40-62.range86-153.btcentralplus.com. [86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=S9F2TYRjFfKeq16EtFZAcuwlp4w8sYp3VCQNDpZ7eDU=; b=B2Z0sUf8KIKgA979/aJhN0wtRJKT/rpcycsNG5WI1PbfCRh4svOTj8BpUB6ZjPB+dp 3d3EPDB9qmkAPQgli7U7YGsd++Ga9TzYrLPhn3d+ygnCRpOCzLOUObCa4iS5iw+qDEJK zIu5NCsthuYoF/bt5jvaQWUeDeqqXtFiiCCrI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=S9F2TYRjFfKeq16EtFZAcuwlp4w8sYp3VCQNDpZ7eDU=; b=J4g2NpmmDSlJWZ6yIBxnVIjCIwP/i7W9Gr82Xd+KyJuzYSv2akJoowOsXICGglEXv8 gh+Q4yd1H+m8AJnIET+RHWMSWeEzl2sPwNEMuvQjhKn5AUqveUIUlv6C0lhbiL6MjJIF +K8QpPC5BCeswYxsUGpc5YIvA/XPjQk+OVjjV3Ucbx05rnm+HPuQB/zVPrfCKePSTkAs S1ZLojmXDMvSSLo/be5g4Wh39VmlBgnoNpQybbxmgxPq36SgVJnooMTX+Cyv8wBvrBna ht92vtc4dRFaSA6q6mtWySeAXMYVkMK2EBlC7/yvFZOAjeEIDCOW2wLkvymsrUPa729H jXsg== X-Gm-Message-State: AGRZ1gKzWKG6dtjF9dnYbXGsJ+ZIAnJN7Jsgvvr/ziQLJfXNMSkL26V2 KQp/Nra3QDxeQDixGzS8OLgDqazdIas= X-Google-Smtp-Source: AJdET5cyKJDb/DOj41exmcOzKk5j5KvVY0bzRPIGRVYGiZgtcwbVi65/nO5n60e5ZuCZX+mgsRndEg== X-Received: by 2002:adf:ed4b:: with SMTP id u11-v6mr9164951wro.236.1540278190009; Tue, 23 Oct 2018 00:03:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:51 +0100 Message-Id: <20181023070253.6407-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 08/10] cputlb: Count "partial" and "elided" tlb flushes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Our only statistic so far was "full" tlb flushes, where all mmu_idx are flushed at the same time. Now count "partial" tlb flushes where sets of mmu_idx are flushed, but the set is not maximal. Account one per mmu_idx flushed, as that is the unit of work performed. We don't actually count elided flushes yet, but go ahead and change the interface presented to the monitor all at once. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 12 ++++++++++-- include/exec/cputlb.h | 2 +- accel/tcg/cputlb.c | 18 +++++++++++++----- accel/tcg/translate-all.c | 8 ++++++-- 4 files changed, 30 insertions(+), 10 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 181c0dbfa4..c7b501d627 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -166,6 +166,15 @@ typedef struct CPUTLBCommon { * mmu_idx may be discarded. Protected by tlb_c.lock. */ uint16_t pending_flush; + + /* + * Statistics. These are not lock protected, but are read and + * written atomically. This allows the monitor to print a snapshot + * of the stats without interfering with the cpu. + */ + size_t full_flush_count; + size_t part_flush_count; + size_t elide_flush_count; } CPUTLBCommon; =20 /* @@ -179,8 +188,7 @@ typedef struct CPUTLBCommon { CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ - CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ - size_t tlb_flush_count; + CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; =20 #else =20 diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index c91db211bc..5373188be3 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -23,6 +23,6 @@ /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -size_t tlb_flush_count(void); +void tlb_flush_counts(size_t *full, size_t *part, size_t *elide); #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4447a5f028..5480115cb4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -100,17 +100,21 @@ static void flush_all_helper(CPUState *src, run_on_cp= u_func fn, } } =20 -size_t tlb_flush_count(void) +void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide) { CPUState *cpu; - size_t count =3D 0; + size_t full =3D 0, part =3D 0, elide =3D 0; =20 CPU_FOREACH(cpu) { CPUArchState *env =3D cpu->env_ptr; =20 - count +=3D atomic_read(&env->tlb_flush_count); + full +=3D atomic_read(&env->tlb_c.full_flush_count); + part +=3D atomic_read(&env->tlb_c.part_flush_count); + elide +=3D atomic_read(&env->tlb_c.elide_flush_count); } - return count; + *pfull =3D full; + *ppart =3D part; + *pelide =3D elide; } =20 static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) @@ -145,7 +149,11 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *c= pu, run_on_cpu_data data) cpu_tb_jmp_cache_clear(cpu); =20 if (mmu_idx_bitmask =3D=3D ALL_MMUIDX_BITS) { - atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + atomic_set(&env->tlb_c.full_flush_count, + env->tlb_c.full_flush_count + 1); + } else { + atomic_set(&env->tlb_c.part_flush_count, + env->tlb_c.part_flush_count + ctpop16(mmu_idx_bitmask)); } } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 356dcd0948..639f0b2728 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2290,7 +2290,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) { struct tb_tree_stats tst =3D {}; struct qht_stats hst; - size_t nb_tbs; + size_t nb_tbs, flush_full, flush_part, flush_elide; =20 tcg_tb_foreach(tb_tree_stats_iter, &tst); nb_tbs =3D tst.nb_tbs; @@ -2326,7 +2326,11 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fp= rintf) cpu_fprintf(f, "TB flush count %u\n", atomic_read(&tb_ctx.tb_flush_count)); cpu_fprintf(f, "TB invalidate count %zu\n", tcg_tb_phys_invalidate_cou= nt()); - cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); + + tlb_flush_counts(&flush_full, &flush_part, &flush_elide); + cpu_fprintf(f, "TLB full flushes %zu\n", flush_full); + cpu_fprintf(f, "TLB partial flushes %zu\n", flush_part); + cpu_fprintf(f, "TLB elided flushes %zu\n", flush_elide); tcg_dump_info(f, cpu_fprintf); } =20 --=20 2.17.2 From nobody Thu Nov 6 08:24:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540278852527863.9065272676778; Tue, 23 Oct 2018 00:14:12 -0700 (PDT) Received: from localhost ([::1]:38506 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqtH-00073U-Ei for importer@patchew.org; Tue, 23 Oct 2018 03:14:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59636) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqm4-0008Od-K8 for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEqif-0003wx-ED for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:18 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:37048) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEqif-0003tb-0g for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:13 -0400 Received: by mail-wm1-x344.google.com with SMTP id x19-v6so544984wmc.2 for ; Tue, 23 Oct 2018 00:03:12 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (host86-153-40-62.range86-153.btcentralplus.com. [86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1hvg9z51OQOp7GSTXVGygTFja2i610PhoH7b+MvaDsk=; b=f7YoFWEET7er4ukkhJkxsohgLimk1Y9IOe2+sXLjVfdeYLycork9fw4il03HbfAd1A hLV+L/YGYwnG+QU0UugQAxxZ0hKkfyFyp4zR7ZnT1W2BwklLg9y/jzNlcdhOf8HDaxCr uQqUseyVqLvnUwuRckJP7Zx1V2Wk/ytz4kNcE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1hvg9z51OQOp7GSTXVGygTFja2i610PhoH7b+MvaDsk=; b=TPRl8jX1GBjuYld2yVgZR2xuOpEphgkcyIwLRmiXJ1qD2P+r6cQW7ltNanIkrjmjTx AEDu/gsGGkimdrbwKfv6+97wZubIY70W4HhZinLK12u5DRrs0fIW5RW8hRa+NHSjOkE4 9OFADhxMKenEGwgfZT9r7VTgqoaFWohztwrRiHmVnHO17pcOSDxNPi2cvcPEZ2pzoAKO j0HgTc0Ji2nSRuumEqrrwB77z7QmaU36RzAih6uKjCXTUzPNyWKu2OVoQ/JWNz6Jm6wW iA2PYzRdQ1WP+Yqyil9tqHXQoBvd6Pjbkl+96eksi8lDxwfkbzMvs/50Z+hEW1598Sgh //xA== X-Gm-Message-State: ABuFfog0f1ADgR/X5s3B99UleugzGsF5/1KAUsyFfknH2wCBhDXO50dO e+shKTpKkf9cSwI9cjmdf7eQ8wUx5iE= X-Google-Smtp-Source: AJdET5eTss3WYNBd4Emrnum/f2mEQMh1MpGnrApq0D4KsNuME2fMHcWXENN0HWoD44hiQBN4ql9X7w== X-Received: by 2002:a1c:1a45:: with SMTP id a66-v6mr2574778wma.20.1540278191300; Tue, 23 Oct 2018 00:03:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:52 +0100 Message-Id: <20181023070253.6407-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 09/10] cputlb: Filter flushes on already clean tlbs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Especially for guests with large numbers of tlbs, like ARM or PPC, we may well not use all of them in between flush operations. Remember which tlbs have been used since the last flush, and avoid any useless flushing. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 7 ++++++- accel/tcg/cputlb.c | 35 +++++++++++++++++++++++++---------- 2 files changed, 31 insertions(+), 11 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index c7b501d627..ca0fea8b27 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -166,7 +166,12 @@ typedef struct CPUTLBCommon { * mmu_idx may be discarded. Protected by tlb_c.lock. */ uint16_t pending_flush; - + /* + * Within dirty, for each bit N, modifications have been made to + * mmu_idx N since the last time that mmu_idx was flushed. + * Protected by tlb_c.lock. + */ + uint16_t dirty; /* * Statistics. These are not lock protected, but are read and * written atomically. This allows the monitor to print a snapshot diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5480115cb4..c1b92083d4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -79,6 +79,9 @@ void tlb_init(CPUState *cpu) CPUArchState *env =3D cpu->env_ptr; =20 qemu_spin_init(&env->tlb_c.lock); + + /* Ensure that cpu_reset performs a full flush. */ + env->tlb_c.dirty =3D ALL_MMUIDX_BITS; } =20 /* flush_all_helper: run fn across all cpus @@ -129,31 +132,40 @@ static void tlb_flush_one_mmuidx_locked(CPUArchState = *env, int mmu_idx) static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data = data) { CPUArchState *env =3D cpu->env_ptr; - unsigned long mmu_idx_bitmask =3D data.host_int; - int mmu_idx; + uint16_t asked =3D data.host_int; + uint16_t all_dirty, work, to_clean; =20 assert_cpu_is_self(cpu); =20 - tlb_debug("mmu_idx:0x%04lx\n", mmu_idx_bitmask); + tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked); =20 qemu_spin_lock(&env->tlb_c.lock); - env->tlb_c.pending_flush &=3D ~mmu_idx_bitmask; =20 - for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - if (test_bit(mmu_idx, &mmu_idx_bitmask)) { - tlb_flush_one_mmuidx_locked(env, mmu_idx); - } + all_dirty =3D env->tlb_c.dirty; + to_clean =3D asked & all_dirty; + all_dirty &=3D ~to_clean; + env->tlb_c.dirty =3D all_dirty; + + for (work =3D to_clean; work !=3D 0; work &=3D work - 1) { + int mmu_idx =3D ctz32(work); + tlb_flush_one_mmuidx_locked(env, mmu_idx); } + qemu_spin_unlock(&env->tlb_c.lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 - if (mmu_idx_bitmask =3D=3D ALL_MMUIDX_BITS) { + if (to_clean =3D=3D ALL_MMUIDX_BITS) { atomic_set(&env->tlb_c.full_flush_count, env->tlb_c.full_flush_count + 1); } else { atomic_set(&env->tlb_c.part_flush_count, - env->tlb_c.part_flush_count + ctpop16(mmu_idx_bitmask)); + env->tlb_c.part_flush_count + ctpop16(to_clean)); + if (to_clean !=3D asked) { + atomic_set(&env->tlb_c.elide_flush_count, + env->tlb_c.elide_flush_count + + ctpop16(asked & ~to_clean)); + } } } =20 @@ -582,6 +594,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, */ qemu_spin_lock(&env->tlb_c.lock); =20 + /* Note that the tlb is no longer clean. */ + env->tlb_c.dirty |=3D 1 << mmu_idx; + /* Make sure there's no cached translation for the new page. */ tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); =20 --=20 2.17.2 From nobody Thu Nov 6 08:24:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540278847794949.9459176976724; Tue, 23 Oct 2018 00:14:07 -0700 (PDT) Received: from localhost ([::1]:38505 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqtC-00072U-DF for importer@patchew.org; Tue, 23 Oct 2018 03:14:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59420) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqm3-0008Nf-HZ for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEqig-0003xk-3E for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:17 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:44866) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEqif-0003wn-S2 for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:14 -0400 Received: by mail-wr1-x444.google.com with SMTP id q6-v6so348027wrw.11 for ; Tue, 23 Oct 2018 00:03:13 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (host86-153-40-62.range86-153.btcentralplus.com. [86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j5xnUIyTOJGIGy9FEJsc6tCQO/KhtXScq8nSq+BVdsM=; b=bwxc7xLLLxDnD7rpffqvrPhnLAKagjQzYbdqUjlh1hJF3Cr1Gmrd8WNaAEQ5ox/65B Zx2lfaIT2mXUREaONSx2ZvXEYN8AM236Kk2bFTBMzYOokVhiGaNzodZdILKohUDUQUPa mxONefrjMhpjbXqfYkNckdNWwCBX1VL3pPu1E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j5xnUIyTOJGIGy9FEJsc6tCQO/KhtXScq8nSq+BVdsM=; b=sRFcr+27ydezjiTOua+qPR95hf1hGIacTOoT4ZxYDQ8UEuLuzWYV7ULstL0wXusZqI 7RhXxtvTGbk5ZOfeygv7QJGHDkv4GJbhPAWFVm2Ck7in6/uYMoevqoI7aiA4EyTORry3 TKGtvGKZ/ZGCMHnqFR6PEzc3aqMz5czsFc9Nu9/AOuJYCiXC31wPwa4YZwC/uLI1IUqH vdUQ0PXqXdijq0AHL7c1dOzDGO32bdqV7IkFRaPoky6xfADzOiOTb6DHRxuEuOMlnaUT q2ZN0esnVdFUUnymf+QFn+f6C3om2IDqo1t0PDMHZGUMuADK7AC3hyUhtFLw73lrQtgl j15g== X-Gm-Message-State: AGRZ1gItTNdhGnhkYgYy3XrrNqCfZCaHYG4g1M7kugY2bb20S3YXByDl DwWZuF+5MxLq7Af/qvrr69acAcSddYM= X-Google-Smtp-Source: AJdET5cGVCD9YnacMfryG1svWA+3rrZGYcur+BvOIg/uW3ZmwC4bzDpSR64a+NiScbRO1DtcSBmjXQ== X-Received: by 2002:adf:9c0a:: with SMTP id f10-v6mr837456wrc.93.1540278192653; Tue, 23 Oct 2018 00:03:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:53 +0100 Message-Id: <20181023070253.6407-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 10/10] cputlb: Remove tlb_c.pending_flushes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is essentially redundant with tlb_c.dirty. [??? Collect data to back up this supposition] Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 6 ------ accel/tcg/cputlb.c | 16 ++-------------- 2 files changed, 2 insertions(+), 20 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ca0fea8b27..6a60f94a41 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -160,12 +160,6 @@ typedef struct CPUTLBDesc { typedef struct CPUTLBCommon { /* Serialize updates to tlb_table and tlb_v_table, and others as noted= . */ QemuSpin lock; - /* - * Within pending_flush, for each bit N, there exists an outstanding - * cross-cpu flush for mmu_idx N. Further cross-cpu flushes to that - * mmu_idx may be discarded. Protected by tlb_c.lock. - */ - uint16_t pending_flush; /* * Within dirty, for each bit N, modifications have been made to * mmu_idx N since the last time that mmu_idx was flushed. diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c1b92083d4..fec37bd3bd 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -174,20 +174,8 @@ void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxma= p) tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap); =20 if (cpu->created && !qemu_cpu_is_self(cpu)) { - CPUArchState *env =3D cpu->env_ptr; - uint16_t pending, to_clean; - - qemu_spin_lock(&env->tlb_c.lock); - pending =3D env->tlb_c.pending_flush; - to_clean =3D idxmap & ~pending; - env->tlb_c.pending_flush =3D pending | idxmap; - qemu_spin_unlock(&env->tlb_c.lock); - - if (to_clean) { - tlb_debug("reduced mmu_idx: 0x%" PRIx16 "\n", to_clean); - async_run_on_cpu(cpu, tlb_flush_by_mmuidx_async_work, - RUN_ON_CPU_HOST_INT(to_clean)); - } + async_run_on_cpu(cpu, tlb_flush_by_mmuidx_async_work, + RUN_ON_CPU_HOST_INT(idxmap)); } else { tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(idxmap)); } --=20 2.17.2 From nobody Thu Nov 6 08:24:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540278725003100.01241045977883; Tue, 23 Oct 2018 00:12:05 -0700 (PDT) Received: from localhost ([::1]:38492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqrD-0004cz-9B for importer@patchew.org; Tue, 23 Oct 2018 03:12:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59938) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqm5-0008QL-1m for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEqid-0003sh-EP for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:17 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:46002) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEqic-0003id-7w for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:11 -0400 Received: by mail-wr1-x442.google.com with SMTP id f17-v6so341630wrs.12 for ; Tue, 23 Oct 2018 00:03:01 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (host86-153-40-62.range86-153.btcentralplus.com. [86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.02.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:02:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Aemm+FkfNxZFuIuM8Lsl0WBJ4No9SI3OzHQ9cbNtZas=; b=MP+KFp5mmz7e2KCoUB9Kwtxxd2dwfOaRFJ1AjYJh15ltU5N0iVsI4kx1A8sxaMEdmk XvuNkTsCEiute7zck15tVfegCTKLq3Bincs0XSMzC5tMLms0dtOCtxjpbQbKKtGGAekJ iir99Uv4yZNfDOKxUzwGGhICug9CB4e7oZvVk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Aemm+FkfNxZFuIuM8Lsl0WBJ4No9SI3OzHQ9cbNtZas=; b=p267jJRCIwDS7K6yc/02G14CjSISe+Jek1z993hzGnMCLYpXfIoj5fFnBbqth1vyO4 pK0mnsQTo1ydNafTYwmgMcy7VeJcAkKIkbGUxH30yp5LpoArwwrLvlG1G+E81ryZVyRu swh805XPGMUxsVfd78cPHDSlQG6Edt9daOVAakf7AWYOEnhSgem4Z+BbVNYTiUuyIDSg H/tPaR2ai10c0N59HUT2j4H9uKZv/HlB5SMxwPZ2hJQFyssr+mEfzJstBKdcUNqU4X73 KtiY4z0fgH1aP3xORDp+DQO0TdlJK1pIv3nHmAvYwHrUPTzGa3tOtAguUhXYFpGv6A9t GHIA== X-Gm-Message-State: ABuFfogMe13KziskCDHttknHT8O9G4D+TWbhA5lM0ehHdxqpJrg0qkTb sPYCHDB1yEGZwsn48YoFzAqajVH5Qcg= X-Google-Smtp-Source: ACcGV60m4TVlvzMId9Ila8iw+s0h5znRO1EQowDdYl66PcL1cPdyIE7WpgvGGgaEDTHvum7AAvdkZg== X-Received: by 2002:adf:ae09:: with SMTP id x9-v6mr47194806wrc.102.1540278179587; Tue, 23 Oct 2018 00:02:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:44 +0100 Message-Id: <20181023070253.6407-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH, build fix] osdep: Work around MinGW assert X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In several places we use assert(FEATURE), and assume that if FEATURE is disabled, all following code is removed as unreachable. Which allows us to compile-out functions that are only present with FEATURE, and have a link-time failure if the functions remain used. MinGW does not mark its internal function _assert() as noreturn, so the compiler cannot see when code is unreachable, which leads to link errors for this host that are not present elsewhere. The current build-time failure concerns 62823083b8a2, but I remember having seen this same error before. Fix it once and for all for MinGW. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/osdep.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 4f8559e550..0c1e335a43 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -122,6 +122,18 @@ extern int daemon(int, int); #include "glib-compat.h" #include "qemu/typedefs.h" =20 +/* + * For mingw, as of v6.0.0, the function implementing the assert macro is + * not marked a noreturn, so the compiler cannot delete code following an + * assert(false) as unused. We rely on this within the code base to delete + * code that is unreachable when features are disabled. + * All supported versions of Glib's g_assert() satisfy this requirement. + */ +#ifdef __MINGW32__ +#undef assert +#define assert(x) g_assert(x) +#endif + /* * According to waitpid man page: * WCOREDUMP --=20 2.17.2