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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 19 Oct 2018 17:57:34 +0100
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Subject: [Qemu-devel] [PULL 44/45] target/arm: Remove writefn from TTBR0_EL3
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From: Richard Henderson <richard.henderson@linaro.org>
The EL3 version of this register does not include an ASID,
and so the tlb_flush performed by vmsa_ttbr_write is not needed.
Reviewed-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20181019015617.22583-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bf4f50196de..20114bf574d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4312,7 +4312,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D {
.fieldoffset =3D offsetof(CPUARMState, cp15.mvbar) },
{ .name =3D "TTBR0_EL3", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 0,
- .access =3D PL3_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0,
+ .access =3D PL3_RW, .resetvalue =3D 0,
.fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[3]) },
{ .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2,
--=20
2.19.1