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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 19 Oct 2018 17:57:29 +0100
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Subject: [Qemu-devel] [PULL 39/45] target/arm: Reorg NEON VLD/VST all
elements
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From: Richard Henderson <richard.henderson@linaro.org>
Instead of shifts and masks, use direct loads and stores from the neon
register file. Mirror the iteration structure of the ARM pseudocode
more closely. Correct the parameters of the VLD2 A2 insn.
Note that this includes a bugfix for handling of the insn
"VLD2 (multiple 2-element structures)" -- we were using an
incorrect stride value.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181011205206.3552-19-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 170 ++++++++++++++++++-----------------------
1 file changed, 74 insertions(+), 96 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e5d723d03b7..7f209b4ae2b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1611,12 +1611,56 @@ static TCGv_i32 neon_load_reg(int reg, int pass)
return tmp;
}
=20
+static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp m=
op)
+{
+ long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE);
+
+ switch (mop) {
+ case MO_UB:
+ tcg_gen_ld8u_i64(var, cpu_env, offset);
+ break;
+ case MO_UW:
+ tcg_gen_ld16u_i64(var, cpu_env, offset);
+ break;
+ case MO_UL:
+ tcg_gen_ld32u_i64(var, cpu_env, offset);
+ break;
+ case MO_Q:
+ tcg_gen_ld_i64(var, cpu_env, offset);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static void neon_store_reg(int reg, int pass, TCGv_i32 var)
{
tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
tcg_temp_free_i32(var);
}
=20
+static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64=
var)
+{
+ long offset =3D neon_element_offset(reg, ele, size);
+
+ switch (size) {
+ case MO_8:
+ tcg_gen_st8_i64(var, cpu_env, offset);
+ break;
+ case MO_16:
+ tcg_gen_st16_i64(var, cpu_env, offset);
+ break;
+ case MO_32:
+ tcg_gen_st32_i64(var, cpu_env, offset);
+ break;
+ case MO_64:
+ tcg_gen_st_i64(var, cpu_env, offset);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static inline void neon_load_reg64(TCGv_i64 var, int reg)
{
tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
@@ -4885,16 +4929,16 @@ static struct {
int interleave;
int spacing;
} const neon_ls_element_type[11] =3D {
- {4, 4, 1},
- {4, 4, 2},
+ {1, 4, 1},
+ {1, 4, 2},
{4, 1, 1},
- {4, 2, 1},
- {3, 3, 1},
- {3, 3, 2},
+ {2, 2, 2},
+ {1, 3, 1},
+ {1, 3, 2},
{3, 1, 1},
{1, 1, 1},
- {2, 2, 1},
- {2, 2, 2},
+ {1, 2, 1},
+ {1, 2, 2},
{2, 1, 1}
};
=20
@@ -4915,6 +4959,8 @@ static int disas_neon_ls_insn(DisasContext *s, uint32=
_t insn)
int shift;
int n;
int vec_size;
+ int mmu_idx;
+ TCGMemOp endian;
TCGv_i32 addr;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -4936,6 +4982,8 @@ static int disas_neon_ls_insn(DisasContext *s, uint32=
_t insn)
rn =3D (insn >> 16) & 0xf;
rm =3D insn & 0xf;
load =3D (insn & (1 << 21)) !=3D 0;
+ endian =3D s->be_data;
+ mmu_idx =3D get_mem_index(s);
if ((insn & (1 << 23)) =3D=3D 0) {
/* Load store all elements. */
op =3D (insn >> 8) & 0xf;
@@ -4960,104 +5008,34 @@ static int disas_neon_ls_insn(DisasContext *s, uin=
t32_t insn)
nregs =3D neon_ls_element_type[op].nregs;
interleave =3D neon_ls_element_type[op].interleave;
spacing =3D neon_ls_element_type[op].spacing;
- if (size =3D=3D 3 && (interleave | spacing) !=3D 1)
+ if (size =3D=3D 3 && (interleave | spacing) !=3D 1) {
return 1;
+ }
+ tmp64 =3D tcg_temp_new_i64();
addr =3D tcg_temp_new_i32();
+ tmp2 =3D tcg_const_i32(1 << size);
load_reg_var(s, addr, rn);
- stride =3D (1 << size) * interleave;
for (reg =3D 0; reg < nregs; reg++) {
- if (interleave > 2 || (interleave =3D=3D 2 && nregs =3D=3D 2))=
{
- load_reg_var(s, addr, rn);
- tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
- } else if (interleave =3D=3D 2 && nregs =3D=3D 4 && reg =3D=3D=
2) {
- load_reg_var(s, addr, rn);
- tcg_gen_addi_i32(addr, addr, 1 << size);
- }
- if (size =3D=3D 3) {
- tmp64 =3D tcg_temp_new_i64();
- if (load) {
- gen_aa32_ld64(s, tmp64, addr, get_mem_index(s));
- neon_store_reg64(tmp64, rd);
- } else {
- neon_load_reg64(tmp64, rd);
- gen_aa32_st64(s, tmp64, addr, get_mem_index(s));
- }
- tcg_temp_free_i64(tmp64);
- tcg_gen_addi_i32(addr, addr, stride);
- } else {
- for (pass =3D 0; pass < 2; pass++) {
- if (size =3D=3D 2) {
- if (load) {
- tmp =3D tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- neon_store_reg(rd, pass, tmp);
- } else {
- tmp =3D neon_load_reg(rd, pass);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- }
- tcg_gen_addi_i32(addr, addr, stride);
- } else if (size =3D=3D 1) {
- if (load) {
- tmp =3D tcg_temp_new_i32();
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
- tcg_gen_addi_i32(addr, addr, stride);
- tmp2 =3D tcg_temp_new_i32();
- gen_aa32_ld16u(s, tmp2, addr, get_mem_index(s)=
);
- tcg_gen_addi_i32(addr, addr, stride);
- tcg_gen_shli_i32(tmp2, tmp2, 16);
- tcg_gen_or_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- neon_store_reg(rd, pass, tmp);
- } else {
- tmp =3D neon_load_reg(rd, pass);
- tmp2 =3D tcg_temp_new_i32();
- tcg_gen_shri_i32(tmp2, tmp, 16);
- gen_aa32_st16(s, tmp, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp);
- tcg_gen_addi_i32(addr, addr, stride);
- gen_aa32_st16(s, tmp2, addr, get_mem_index(s));
- tcg_temp_free_i32(tmp2);
- tcg_gen_addi_i32(addr, addr, stride);
- }
- } else /* size =3D=3D 0 */ {
- if (load) {
- tmp2 =3D NULL;
- for (n =3D 0; n < 4; n++) {
- tmp =3D tcg_temp_new_i32();
- gen_aa32_ld8u(s, tmp, addr, get_mem_index(=
s));
- tcg_gen_addi_i32(addr, addr, stride);
- if (n =3D=3D 0) {
- tmp2 =3D tmp;
- } else {
- tcg_gen_shli_i32(tmp, tmp, n * 8);
- tcg_gen_or_i32(tmp2, tmp2, tmp);
- tcg_temp_free_i32(tmp);
- }
- }
- neon_store_reg(rd, pass, tmp2);
- } else {
- tmp2 =3D neon_load_reg(rd, pass);
- for (n =3D 0; n < 4; n++) {
- tmp =3D tcg_temp_new_i32();
- if (n =3D=3D 0) {
- tcg_gen_mov_i32(tmp, tmp2);
- } else {
- tcg_gen_shri_i32(tmp, tmp2, n * 8);
- }
- gen_aa32_st8(s, tmp, addr, get_mem_index(s=
));
- tcg_temp_free_i32(tmp);
- tcg_gen_addi_i32(addr, addr, stride);
- }
- tcg_temp_free_i32(tmp2);
- }
+ for (n =3D 0; n < 8 >> size; n++) {
+ int xs;
+ for (xs =3D 0; xs < interleave; xs++) {
+ int tt =3D rd + reg + spacing * xs;
+
+ if (load) {
+ gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | =
size);
+ neon_store_element64(tt, n, size, tmp64);
+ } else {
+ neon_load_element64(tmp64, tt, n, size);
+ gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | =
size);
}
+ tcg_gen_add_i32(addr, addr, tmp2);
}
}
- rd +=3D spacing;
}
tcg_temp_free_i32(addr);
- stride =3D nregs * 8;
+ tcg_temp_free_i32(tmp2);
+ tcg_temp_free_i64(tmp64);
+ stride =3D nregs * interleave * 8;
} else {
size =3D (insn >> 10) & 3;
if (size =3D=3D 3) {
--=20
2.19.1