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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 19 Oct 2018 17:57:23 +0100
Message-Id: <20181019165735.22511-34-peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 33/45] target/arm: Use gvec for VSHR, VSHL
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From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181011205206.3552-13-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 70 +++++++++++++++++++++++++++++-------------
1 file changed, 48 insertions(+), 22 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7b13717c0dc..2d715d9b47b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6373,8 +6373,6 @@ static int disas_neon_data_insn(DisasContext *s, uint=
32_t insn)
size--;
}
shift =3D (insn >> 16) & ((1 << (3 + size)) - 1);
- /* To avoid excessive duplication of ops we implement shift
- by immediate using the variable shift operations. */
if (op < 8) {
/* Shift by immediate:
VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
@@ -6386,37 +6384,62 @@ static int disas_neon_data_insn(DisasContext *s, ui=
nt32_t insn)
}
/* Right shifts are encoded as N - shift, where N is the
element size in bits. */
- if (op <=3D 4)
+ if (op <=3D 4) {
shift =3D shift - (1 << (size + 3));
+ }
+
+ switch (op) {
+ case 0: /* VSHR */
+ /* Right shift comes here negative. */
+ shift =3D -shift;
+ /* Shifts larger than the element size are architectur=
ally
+ * valid. Unsigned results in all zeros; signed resul=
ts
+ * in all sign bits.
+ */
+ if (!u) {
+ tcg_gen_gvec_sari(size, rd_ofs, rm_ofs,
+ MIN(shift, (8 << size) - 1),
+ vec_size, vec_size);
+ } else if (shift >=3D 8 << size) {
+ tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
+ } else {
+ tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
+ vec_size, vec_size);
+ }
+ return 0;
+
+ case 5: /* VSHL, VSLI */
+ if (!u) { /* VSHL */
+ /* Shifts larger than the element size are
+ * architecturally valid and results in zero.
+ */
+ if (shift >=3D 8 << size) {
+ tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size,=
0);
+ } else {
+ tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
+ vec_size, vec_size);
+ }
+ return 0;
+ }
+ break;
+ }
+
if (size =3D=3D 3) {
count =3D q + 1;
} else {
count =3D q ? 4: 2;
}
- switch (size) {
- case 0:
- imm =3D (uint8_t) shift;
- imm |=3D imm << 8;
- imm |=3D imm << 16;
- break;
- case 1:
- imm =3D (uint16_t) shift;
- imm |=3D imm << 16;
- break;
- case 2:
- case 3:
- imm =3D shift;
- break;
- default:
- abort();
- }
+
+ /* To avoid excessive duplication of ops we implement shift
+ * by immediate using the variable shift operations.
+ */
+ imm =3D dup_const(size, shift);
=20
for (pass =3D 0; pass < count; pass++) {
if (size =3D=3D 3) {
neon_load_reg64(cpu_V0, rm + pass);
tcg_gen_movi_i64(cpu_V1, imm);
switch (op) {
- case 0: /* VSHR */
case 1: /* VSRA */
if (u)
gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cp=
u_V1);
@@ -6447,6 +6470,8 @@ static int disas_neon_data_insn(DisasContext *s, uint=
32_t insn)
cpu_V0, cpu_V1);
}
break;
+ default:
+ g_assert_not_reached();
}
if (op =3D=3D 1 || op =3D=3D 3) {
/* Accumulate. */
@@ -6475,7 +6500,6 @@ static int disas_neon_data_insn(DisasContext *s, uint=
32_t insn)
tmp2 =3D tcg_temp_new_i32();
tcg_gen_movi_i32(tmp2, imm);
switch (op) {
- case 0: /* VSHR */
case 1: /* VSRA */
GEN_NEON_INTEGER_OP(shl);
break;
@@ -6513,6 +6537,8 @@ static int disas_neon_data_insn(DisasContext *s, uint=
32_t insn)
case 7: /* VQSHL */
GEN_NEON_INTEGER_OP_ENV(qshl);
break;
+ default:
+ g_assert_not_reached();
}
tcg_temp_free_i32(tmp2);
=20
--=20
2.19.1