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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 19 Oct 2018 17:57:18 +0100
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Subject: [Qemu-devel] [PULL 28/45] target/arm: Use gvec for NEON VMOV, VMVN,
VBIC & VORR (immediate)
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From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181011205206.3552-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 67 ++++++++++++++++++++++++------------------
1 file changed, 39 insertions(+), 28 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6fcc43f25c7..7cc0c76420f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6641,7 +6641,8 @@ static int disas_neon_data_insn(DisasContext *s, uint=
32_t insn)
return 1;
}
} else { /* (insn & 0x00380080) =3D=3D 0 */
- int invert;
+ int invert, reg_ofs, vec_size;
+
if (q && (rd & 1)) {
return 1;
}
@@ -6681,8 +6682,9 @@ static int disas_neon_data_insn(DisasContext *s, uint=
32_t insn)
break;
case 14:
imm |=3D (imm << 8) | (imm << 16) | (imm << 24);
- if (invert)
+ if (invert) {
imm =3D ~imm;
+ }
break;
case 15:
if (invert) {
@@ -6692,36 +6694,45 @@ static int disas_neon_data_insn(DisasContext *s, ui=
nt32_t insn)
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
break;
}
- if (invert)
+ if (invert) {
imm =3D ~imm;
+ }
=20
- for (pass =3D 0; pass < (q ? 4 : 2); pass++) {
- if (op & 1 && op < 12) {
- tmp =3D neon_load_reg(rd, pass);
- if (invert) {
- /* The immediate value has already been inverted, =
so
- BIC becomes AND. */
- tcg_gen_andi_i32(tmp, tmp, imm);
- } else {
- tcg_gen_ori_i32(tmp, tmp, imm);
- }
+ reg_ofs =3D neon_reg_offset(rd, 0);
+ vec_size =3D q ? 16 : 8;
+
+ if (op & 1 && op < 12) {
+ if (invert) {
+ /* The immediate value has already been inverted,
+ * so BIC becomes AND.
+ */
+ tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm,
+ vec_size, vec_size);
} else {
- /* VMOV, VMVN. */
- tmp =3D tcg_temp_new_i32();
- if (op =3D=3D 14 && invert) {
- int n;
- uint32_t val;
- val =3D 0;
- for (n =3D 0; n < 4; n++) {
- if (imm & (1 << (n + (pass & 1) * 4)))
- val |=3D 0xff << (n * 8);
- }
- tcg_gen_movi_i32(tmp, val);
- } else {
- tcg_gen_movi_i32(tmp, imm);
- }
+ tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm,
+ vec_size, vec_size);
+ }
+ } else {
+ /* VMOV, VMVN. */
+ if (op =3D=3D 14 && invert) {
+ TCGv_i64 t64 =3D tcg_temp_new_i64();
+
+ for (pass =3D 0; pass <=3D q; ++pass) {
+ uint64_t val =3D 0;
+ int n;
+
+ for (n =3D 0; n < 8; n++) {
+ if (imm & (1 << (n + pass * 8))) {
+ val |=3D 0xffull << (n * 8);
+ }
+ }
+ tcg_gen_movi_i64(t64, val);
+ neon_store_reg64(t64, rd + pass);
+ }
+ tcg_temp_free_i64(t64);
+ } else {
+ tcg_gen_gvec_dup32i(reg_ofs, vec_size, vec_size, imm);
}
- neon_store_reg(rd, pass, tmp);
}
}
} else { /* (insn & 0x00800010 =3D=3D 0x00800000) */
--=20
2.19.1