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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 19 Oct 2018 17:57:12 +0100
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Subject: [Qemu-devel] [PULL 22/45] target/arm: Hoist address increment for
vector memory ops
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From: Richard Henderson <rth@twiddle.net>
This can reduce the number of opcodes required for certain
complex forms of load-multiple (e.g. ld4.16b).
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id: 20181011205206.3552-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 09c7c4af047..371909620bb 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3012,7 +3012,7 @@ static void disas_ldst_multiple_struct(DisasContext *=
s, uint32_t insn)
bool is_store =3D !extract32(insn, 22, 1);
bool is_postidx =3D extract32(insn, 23, 1);
bool is_q =3D extract32(insn, 30, 1);
- TCGv_i64 tcg_addr, tcg_rn;
+ TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
=20
int ebytes =3D 1 << size;
int elements =3D (is_q ? 128 : 64) / (8 << size);
@@ -3077,6 +3077,7 @@ static void disas_ldst_multiple_struct(DisasContext *=
s, uint32_t insn)
tcg_rn =3D cpu_reg_sp(s, rn);
tcg_addr =3D tcg_temp_new_i64();
tcg_gen_mov_i64(tcg_addr, tcg_rn);
+ tcg_ebytes =3D tcg_const_i64(ebytes);
=20
for (r =3D 0; r < rpt; r++) {
int e;
@@ -3101,7 +3102,7 @@ static void disas_ldst_multiple_struct(DisasContext *=
s, uint32_t insn)
clear_vec_high(s, is_q, tt);
}
}
- tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
+ tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes);
tt =3D (tt + 1) % 32;
}
}
@@ -3115,6 +3116,7 @@ static void disas_ldst_multiple_struct(DisasContext *=
s, uint32_t insn)
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
}
}
+ tcg_temp_free_i64(tcg_ebytes);
tcg_temp_free_i64(tcg_addr);
}
=20
@@ -3157,7 +3159,7 @@ static void disas_ldst_single_struct(DisasContext *s,=
uint32_t insn)
bool replicate =3D false;
int index =3D is_q << 3 | S << 2 | size;
int ebytes, xs;
- TCGv_i64 tcg_addr, tcg_rn;
+ TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
=20
switch (scale) {
case 3:
@@ -3210,6 +3212,7 @@ static void disas_ldst_single_struct(DisasContext *s,=
uint32_t insn)
tcg_rn =3D cpu_reg_sp(s, rn);
tcg_addr =3D tcg_temp_new_i64();
tcg_gen_mov_i64(tcg_addr, tcg_rn);
+ tcg_ebytes =3D tcg_const_i64(ebytes);
=20
for (xs =3D 0; xs < selem; xs++) {
if (replicate) {
@@ -3252,7 +3255,7 @@ static void disas_ldst_single_struct(DisasContext *s,=
uint32_t insn)
do_vec_st(s, rt, index, tcg_addr, scale);
}
}
- tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
+ tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes);
rt =3D (rt + 1) % 32;
}
=20
@@ -3264,6 +3267,7 @@ static void disas_ldst_single_struct(DisasContext *s,=
uint32_t insn)
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
}
}
+ tcg_temp_free_i64(tcg_ebytes);
tcg_temp_free_i64(tcg_addr);
}
=20
--=20
2.19.1