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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 19 Oct 2018 17:57:07 +0100
Message-Id: <20181019165735.22511-18-peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 17/45] target/arm: Implement HCR.PTW
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If the HCR_EL2 PTW virtualizaiton configuration register bit
is set, then this means that a stage 2 Permission fault must
be generated if a stage 1 translation table access is made
to an address that is mapped as Device memory in stage 2.
Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181012144235.19646-8-peter.maydell@linaro.org
---
target/arm/helper.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index af2f63c31b0..1928d3fadd9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9141,9 +9141,20 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARM=
MMUIdx mmu_idx,
hwaddr s2pa;
int s2prot;
int ret;
+ ARMCacheAttrs cacheattrs =3D {};
+ ARMCacheAttrs *pcacheattrs =3D NULL;
+
+ if (env->cp15.hcr_el2 & HCR_PTW) {
+ /*
+ * PTW means we must fault if this S1 walk touches S2 Device
+ * memory; otherwise we don't care about the attributes and can
+ * save the S2 translation the effort of computing them.
+ */
+ pcacheattrs =3D &cacheattrs;
+ }
=20
ret =3D get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
- &txattrs, &s2prot, &s2size, fi, NULL);
+ &txattrs, &s2prot, &s2size, fi, pcacheatt=
rs);
if (ret) {
assert(fi->type !=3D ARMFault_None);
fi->s2addr =3D addr;
@@ -9151,6 +9162,14 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARM=
MMUIdx mmu_idx,
fi->s1ptw =3D true;
return ~0;
}
+ if (pcacheattrs && (pcacheattrs->attrs & 0xf0) =3D=3D 0) {
+ /* Access was to Device memory: generate Permission fault */
+ fi->type =3D ARMFault_Permission;
+ fi->s2addr =3D addr;
+ fi->stage2 =3D true;
+ fi->s1ptw =3D true;
+ return ~0;
+ }
addr =3D s2pa;
}
return addr;
--=20
2.19.1