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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 19 Oct 2018 17:57:06 +0100
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Subject: [Qemu-devel] [PULL 16/45] target/arm: Implement HCR.VI and VF
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The HCR_EL2 VI and VF bits are supposed to track whether there is
a pending virtual IRQ or virtual FIQ. For QEMU we store the
pending VIRQ/VFIQ status in cs->interrupt_request, so this means:
* if the register is read we must get these bit values from
cs->interrupt_request
* if the register is written then we must write the bit
values back into cs->interrupt_request
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181012144235.19646-7-peter.maydell@linaro.org
---
target/arm/helper.c | 47 +++++++++++++++++++++++++++++++++++++++++----
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0ecef3c1360..af2f63c31b0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3931,6 +3931,7 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] =
=3D {
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v=
alue)
{
ARMCPU *cpu =3D arm_env_get_cpu(env);
+ CPUState *cs =3D ENV_GET_CPU(env);
uint64_t valid_mask =3D HCR_MASK;
=20
if (arm_feature(env, ARM_FEATURE_EL3)) {
@@ -3949,6 +3950,28 @@ static void hcr_write(CPUARMState *env, const ARMCPR=
egInfo *ri, uint64_t value)
/* Clear RES0 bits. */
value &=3D valid_mask;
=20
+ /*
+ * VI and VF are kept in cs->interrupt_request. Modifying that
+ * requires that we have the iothread lock, which is done by
+ * marking the reginfo structs as ARM_CP_IO.
+ * Note that if a write to HCR pends a VIRQ or VFIQ it is never
+ * possible for it to be taken immediately, because VIRQ and
+ * VFIQ are masked unless running at EL0 or EL1, and HCR
+ * can only be written at EL2.
+ */
+ g_assert(qemu_mutex_iothread_locked());
+ if (value & HCR_VI) {
+ cs->interrupt_request |=3D CPU_INTERRUPT_VIRQ;
+ } else {
+ cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ;
+ }
+ if (value & HCR_VF) {
+ cs->interrupt_request |=3D CPU_INTERRUPT_VFIQ;
+ } else {
+ cs->interrupt_request &=3D ~CPU_INTERRUPT_VFIQ;
+ }
+ value &=3D ~(HCR_VI | HCR_VF);
+
/* These bits change the MMU setup:
* HCR_VM enables stage 2 translation
* HCR_PTW forbids certain page-table setups
@@ -3976,16 +3999,32 @@ static void hcr_writelow(CPUARMState *env, const AR=
MCPRegInfo *ri,
hcr_write(env, NULL, value);
}
=20
+static uint64_t hcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ /* The VI and VF bits live in cs->interrupt_request */
+ uint64_t ret =3D env->cp15.hcr_el2 & ~(HCR_VI | HCR_VF);
+ CPUState *cs =3D ENV_GET_CPU(env);
+
+ if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
+ ret |=3D HCR_VI;
+ }
+ if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
+ ret |=3D HCR_VF;
+ }
+ return ret;
+}
+
static const ARMCPRegInfo el2_cp_reginfo[] =3D {
{ .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64,
+ .type =3D ARM_CP_IO,
.opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0,
.access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_=
el2),
- .writefn =3D hcr_write },
+ .writefn =3D hcr_write, .readfn =3D hcr_read },
{ .name =3D "HCR", .state =3D ARM_CP_STATE_AA32,
- .type =3D ARM_CP_ALIAS,
+ .type =3D ARM_CP_ALIAS | ARM_CP_IO,
.cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0,
.access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_=
el2),
- .writefn =3D hcr_writelow },
+ .writefn =3D hcr_writelow, .readfn =3D hcr_read },
{ .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64,
.type =3D ARM_CP_ALIAS,
.opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1,
@@ -4222,7 +4261,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D {
=20
static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D {
{ .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32,
- .type =3D ARM_CP_ALIAS,
+ .type =3D ARM_CP_ALIAS | ARM_CP_IO,
.cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4,
.access =3D PL2_RW,
.fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2),
--=20
2.19.1