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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id q24-v6sm25609327pff.83.2018.10.18.23.07.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 23:07:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zVQf3itjUOUB22zOcMjuOXnhRpsEU/kH0zSYaIqDkiI=; b=ND1XmovpR7BnqJvMZ4sjIEVBI0wOJImrKaSmN5sGlEz9nG9ibgNWwzXfGnyRYKDzjO dL98ia6kqUtWJ5m5ZQppcq9uVjC7mv+vpDfp14pq0xvqAoP7S5cK5XGgWq2Wiro5efjj f+y4YTXKJA9fO1airpMWI+1DUGH5daB4gtZjU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zVQf3itjUOUB22zOcMjuOXnhRpsEU/kH0zSYaIqDkiI=; b=CDuyI02s6Uj7Xpi+dj1HdQ8nU7CiaL2naqPqsA17GOusX4AXsXUFcSsF3Sp7baK8yE HZA47zpeIJuSyGVn6E3qniNUs/XmIKorPOMon5owHjH0hOyh7431IW+1QT1xX5vOKuED 80OGFvhHBqrcH3iBuXFLPT2nipa36CMbJjW+Hb099XxAkjZBkudLJLHkYhqQJ189Ndiz DikBUDHdtqaAyK9uW7hQQCLYmce++KLX93kFy26aOdyaesi+beBGERq5sC1GhwvA/P9f Cb2xjWAEp7Z0Ui4bj182RXnNO4bqScoQczy+DnAQhz9Gv37chsAldHvOYbM4Ye2QWM9/ DUFw== X-Gm-Message-State: ABuFfoi91iq3TDwzk3tj+EuVXalUo8z5d58eip/kPG77xYxkTFQzn6DH amvs2hsP/Lur6hqNWAGS10rXJCFJ+ZY= X-Google-Smtp-Source: ACcGV61rgssxZq07w1ugiFffMNGpphX2WaT6eVuG856gMhVN8hxVobabDBpldyHP+94iswbdGQ6ZHA== X-Received: by 2002:a17:902:8205:: with SMTP id x5-v6mr33158334pln.55.1539929239100; Thu, 18 Oct 2018 23:07:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 23:06:50 -0700 Message-Id: <20181019060656.7968-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181019060656.7968-1-richard.henderson@linaro.org> References: <20181019060656.7968-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::631 Subject: [Qemu-devel] [PULL v2 15/21] target/arm: Check HAVE_CMPXCHG128 at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Reviewed-by: Emilio G. Cota Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 16 ++++------------ target/arm/translate-a64.c | 38 ++++++++++++++++++++++---------------- 2 files changed, 26 insertions(+), 28 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 6e4e1b8a19..61799d20e1 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -563,9 +563,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMSta= te *env, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); @@ -635,9 +633,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMSta= te *env, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); @@ -663,9 +659,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); @@ -686,9 +680,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8a24278d79..bb9c4d8ac7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -37,6 +37,7 @@ =20 #include "trace-tcg.h" #include "translate-a64.h" +#include "qemu/atomic128.h" =20 static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; @@ -2086,26 +2087,27 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); - } else if (s->be_data =3D=3D MO_LE) { - if (tb_cflags(s->base.tb) & CF_PARALLEL) { + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (!HAVE_CMPXCHG128) { + gen_helper_exit_atomic(cpu_env); + s->base.is_jmp =3D DISAS_NORETURN; + } else if (s->be_data =3D=3D MO_LE) { gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, cpu_exclusive_addr, cpu_reg(s, rt), cpu_reg(s, rt2)); } else { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive= _addr, - cpu_reg(s, rt), cpu_reg(s, = rt2)); - } - } else { - if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, cpu_exclusive_addr, cpu_reg(s, rt), cpu_reg(s, rt2)); - } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive= _addr, - cpu_reg(s, rt), cpu_reg(s, = rt2)); } + } else if (s->be_data =3D=3D MO_LE) { + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_add= r, + cpu_reg(s, rt), cpu_reg(s, rt2)= ); + } else { + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_add= r, + cpu_reg(s, rt), cpu_reg(s, rt2)= ); } } else { tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_= val, @@ -2175,14 +2177,18 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, } tcg_temp_free_i64(cmp); } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - TCGv_i32 tcg_rs =3D tcg_const_i32(rs); - - if (s->be_data =3D=3D MO_LE) { - gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2); + if (HAVE_CMPXCHG128) { + TCGv_i32 tcg_rs =3D tcg_const_i32(rs); + if (s->be_data =3D=3D MO_LE) { + gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2); + } else { + gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2); + } + tcg_temp_free_i32(tcg_rs); } else { - gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2); + gen_helper_exit_atomic(cpu_env); + s->base.is_jmp =3D DISAS_NORETURN; } - tcg_temp_free_i32(tcg_rs); } else { TCGv_i64 d1 =3D tcg_temp_new_i64(); TCGv_i64 d2 =3D tcg_temp_new_i64(); --=20 2.17.2