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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id p62-v6sm33170892pfp.111.2018.10.18.18.56.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 18:56:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TTyR7xzj+PHD0K1CpzmCfsJOcm4+gyZaOYvrOzDqHOk=; b=Ur3D5KVOArDHnTltp5LUYGWt/ZgIi4veW0Z/25r99dmNsARdzSXsivr/7hPOZvmcod 8MIsMOAGSlsxszHGMKrvL+e457nG94IGEs9l7cAiMYojO51ahUBCPEssAxw1fk8IezCF kX/MXTdkaZxuJT3VwFXrIG9je/WCQt9dhlsjM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TTyR7xzj+PHD0K1CpzmCfsJOcm4+gyZaOYvrOzDqHOk=; b=ED1CSg7n2oKzELxuDaMzBlRlRgUnAgab8prl8i4OqE8Z7FnaAxAtzXD26iqWEyiCLr YOQ7pIOTZS0F7+ilgcf89jCs/raYsz08/K5ExnDgHEhWN0EfbLL/wMqM3m8AXZBjOE6Z j9jMwteEiHq8CH7MNr53+IBrwR67USXKI4NSBQZbpAeOJY9GScwfBft8m42oZEE57PVU 2bZzMvV3qc3ClXHe5RJsvIAVkQmwFwKJAB3L27Xy3z6ZrD/HvBPzVA0YaAaBXzGFS2li Tum8o2HfpH5ECpIa4aagxuLwmvQ2TIGskB4xU5LlZxI5RliKBijEu0Khky9L3L9uWISE S5hw== X-Gm-Message-State: ABuFfogV4AGJSkZmROjFp7hTr/M6fbMvJWL+44a6iTY/C3CSnipOLp9X RZCXEpzRbL2IYltuS/9jspZxwczvLHE= X-Google-Smtp-Source: ACcGV60pmkqMOZK9TLSlj88QcVU80US8NNA7E/wybM4DmgIOw1T7bZkpOSwOuqIWXzyQpTr92onetQ== X-Received: by 2002:a65:4783:: with SMTP id e3-v6mr30119517pgs.12.1539914184460; Thu, 18 Oct 2018 18:56:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 18:56:17 -0700 Message-Id: <20181019015617.22583-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181019015617.22583-1-richard.henderson@linaro.org> References: <20181019015617.22583-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 3/3] target/arm: Flush only the TLBs affected by TTBR*_EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Only the EL0 and EL1 TLBs are affected by the EL1 register, so flush only 2 of the 8 TLBs. In testing a boot of the Ubuntu installer to the first menu, this accounts for nearly all of the full tlb flushes: all but 11k of the 1.2M instances without the patch. Signed-off-by: Richard Henderson --- target/arm/helper.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ed70ac645e..3ba8e66487 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2706,14 +2706,16 @@ static void vmsa_tcr_el1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, tcr->raw_tcr =3D value; } =20 -static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void vmsa_ttbr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ if (cpreg_field_is_64bit(ri) && extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { ARMCPU *cpu =3D arm_env_get_cpu(env); - tlb_flush(CPU(cpu)); + tlb_flush_by_mmuidx(CPU(cpu), + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); } raw_write(env, ri, value); } @@ -2761,12 +2763,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr_el1_write, .resetvalue = =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr_el1_write, .resetvalue = =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, @@ -3018,12 +3020,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_el1_write, }, { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_el1_write, }, REGINFO_SENTINEL }; =20 --=20 2.17.2