From nobody Mon Feb 9 21:21:06 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539913288105867.6503649040814; Thu, 18 Oct 2018 18:41:28 -0700 (PDT) Received: from localhost ([::1]:46089 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDJn4-0001xz-T4 for importer@patchew.org; Thu, 18 Oct 2018 21:41:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59301) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDJFo-0004sw-7v for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:07:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDJFk-0003MD-9G for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:07:03 -0400 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:44501) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDJFj-00033Z-Mu for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:06:59 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2B0022297F; Thu, 18 Oct 2018 21:06:35 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Thu, 18 Oct 2018 21:06:35 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id C89E7102E4; Thu, 18 Oct 2018 21:06:34 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=GMCrnjeyzGtITEHb5B7aUEeXbl5vOHjJrndThk57gFQ=; b=DD7o9 VXX4qhxMxyXM1oS30CEUhytMIN2b0PhCTLeGDxxlI7VA38GDbBxQI/jDKz3AQkQs vbiH9RvU+YbMeKSuDEpHcB0PEHC5hDyV+DRqa91JF4U2XtvOgwWNjYOqG5GOJabL TvL2IrIx7z5VMHuyrUNuGw/lnioDi0IyfJuZ4E= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; bh=GMCrnjeyzGtITEHb5B7aUEeXbl5vO HjJrndThk57gFQ=; b=ymNSswv04kF2/l23X8rHellWbV0FEDO+4N8vRoel4IhqW UE6BtL6phHrJtvjQKWTqRJoNvvp6TF2zQ2MlbZxk1lT9IXPj1lB6NVoeK2o9+SDZ X1ay98nia0IUoLldv2Gl69z+HxRmVCgG9RDIaVxoRtx2Tcr7eYnQg/x6qtdePfYI sygMBkvrSLbA7Tz70wfX6xZz6Vho84OGbR4FJF9jSuXRYtc67Vdo/x13MY4LmIrP B6D4992ng91wKWgy8LdAngf72jo/+XaGkuj9qscA/LjarfBi5BMwjdiKptPYUDwP yH8OuXtCd9QuwPrusMM/UPV3bvAuCfF8mpes96vFw== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 21:06:09 -0400 Message-Id: <20181019010625.25294-41-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181019010625.25294-1-cota@braap.org> References: <20181019010625.25294-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.29 Subject: [Qemu-devel] [RFC v3 40/56] alpha: convert to cpu_interrupt_request X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Richard Henderson Signed-off-by: Emilio G. Cota --- target/alpha/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index a953897fcc..4e8965fb6c 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -42,10 +42,10 @@ static bool alpha_cpu_has_work(CPUState *cs) assume that if a CPU really wants to stay asleep, it will mask interrupts at the chipset level, which will prevent these bits from being set in the first place. */ - return cs->interrupt_request & (CPU_INTERRUPT_HARD - | CPU_INTERRUPT_TIMER - | CPU_INTERRUPT_SMP - | CPU_INTERRUPT_MCHK); + return cpu_interrupt_request(cs) & (CPU_INTERRUPT_HARD + | CPU_INTERRUPT_TIMER + | CPU_INTERRUPT_SMP + | CPU_INTERRUPT_MCHK); } =20 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) --=20 2.17.1