From nobody Mon Feb 9 01:20:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539893487467356.43064506786015; Thu, 18 Oct 2018 13:11:27 -0700 (PDT) Received: from localhost ([::1]:44297 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDEdh-0004nR-T0 for importer@patchew.org; Thu, 18 Oct 2018 16:11:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38886) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDEYC-0008Ds-DP for qemu-devel@nongnu.org; Thu, 18 Oct 2018 16:05:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDEYB-0008D6-H0 for qemu-devel@nongnu.org; Thu, 18 Oct 2018 16:05:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59918) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDEY9-00086o-81; Thu, 18 Oct 2018 16:05:41 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E4C283082B4C; Thu, 18 Oct 2018 20:05:39 +0000 (UTC) Received: from localhost (ovpn-117-52.phx2.redhat.com [10.3.117.52]) by smtp.corp.redhat.com (Postfix) with ESMTP id 848AF60160; Thu, 18 Oct 2018 20:05:32 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 17:03:48 -0300 Message-Id: <20181018200422.4358-12-ehabkost@redhat.com> In-Reply-To: <20181018200422.4358-1-ehabkost@redhat.com> References: <20181018200422.4358-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.45]); Thu, 18 Oct 2018 20:05:40 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 11/45] hw/mips/gt64xxx_pci: Convert gt64120_reset() function into Device reset method X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" , libvir-list@redhat.com, Jason Wang , Mark Cave-Ayland , Markus Armbruster , Max Filippov , "Edgar E. Iglesias" , Rob Herring , Alexander Graf , Richard Henderson , Artyom Tarasenko , Eduardo Habkost , Alistair Francis , qemu-arm@nongnu.org, Paolo Bonzini , David Gibson , Xiao Guangrong , Peter Crosthwaite , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Walle , qemu-ppc@nongnu.org, Aleksandar Markovic , Igor Mammedov , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Philippe Mathieu-Daud=C3=A9 Convert the gt64120_reset() function into a proper Device reset method. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20181002212522.23303-8-f4bug@amsat.org> Signed-off-by: Eduardo Habkost --- hw/mips/gt64xxx_pci.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 24ad0ad024..dcd1a66329 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -992,9 +992,9 @@ static void gt64120_pci_set_irq(void *opaque, int irq_n= um, int level) } =20 =20 -static void gt64120_reset(void *opaque) +static void gt64120_reset(DeviceState *dev) { - GT64120State *s =3D opaque; + GT64120State *s =3D GT64120_PCI_HOST_BRIDGE(dev); =20 /* FIXME: Malta specific hw assumptions ahead */ =20 @@ -1184,16 +1184,6 @@ PCIBus *gt64120_register(qemu_irq *pic) return phb->bus; } =20 -static int gt64120_init(SysBusDevice *dev) -{ - GT64120State *s; - - s =3D GT64120_PCI_HOST_BRIDGE(dev); - - qemu_register_reset(gt64120_reset, s); - return 0; -} - static void gt64120_pci_realize(PCIDevice *d, Error **errp) { /* FIXME: Malta specific hw assumptions ahead */ @@ -1241,9 +1231,8 @@ static const TypeInfo gt64120_pci_info =3D { static void gt64120_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); - SysBusDeviceClass *sdc =3D SYS_BUS_DEVICE_CLASS(klass); =20 - sdc->init =3D gt64120_init; + dc->reset =3D gt64120_reset; dc->vmsd =3D &vmstate_gt64120; } =20 --=20 2.18.0.rc1.1.g3f1ff2140