From nobody Wed May 1 23:03:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539887565804526.7876446285096; Thu, 18 Oct 2018 11:32:45 -0700 (PDT) Received: from localhost ([::1]:43786 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDD6C-0004yQ-KL for importer@patchew.org; Thu, 18 Oct 2018 14:32:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37325) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDD1i-000231-9w for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:28:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDD1g-00006V-8C for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:28:06 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:44191) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gDD1f-0008VL-UC for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:28:04 -0400 Received: by mail-pl1-x644.google.com with SMTP id d23-v6so1248996pls.11 for ; Thu, 18 Oct 2018 11:28:03 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id d187-v6sm4795738pfc.13.2018.10.18.11.28.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 11:28:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cG+M4f15Qyl1siFY1/s1Wd/xk37msYwrgv+4KODvxkI=; b=RHRRlS7eSYSfsnA7pepH4Jg7mTglOumxdbYqY9DGq5UPLD5TQhfKMCp+SdE0USZrAq M1y94SV2PRKgeLCqyJWV7Qnu5JiHw858u1uD05BYzQiAm3L0KBhPNT+45KhKYNZN38Gh yR7cAOhCLGo2aGNLyiQxNF2s5OXCfU7pEpqgA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cG+M4f15Qyl1siFY1/s1Wd/xk37msYwrgv+4KODvxkI=; b=RRkspSpj7sa7ziDtKFgptaWIsrPTVzs7BPSu16V3oZj8lLYZu3ZyHuXyzBS8tbsfVb xZSkhWxAokwFVMWyBE2ltNjFyZr+OiUwfjkgxd+5+WTH9GyvYhiHYA5SQynv+bs8iDr2 BW8vG4rtmXF5jw8T7sPdt5ecNPGwDlyWAi1R6tM/5vg+bo3l8lcfzDHbeibXLy7PqeHH 4fXu+wmqZSndmWW1T2jsVGbdThjdXsUKClbx3Pexx1BG8KpSlf4jHN7K95PFOK/jv854 9JWSK43+Dix2y5rc7f82lBqT0YS4v124rtc7JFSZQGFnj5p8fvSWMusXUjsuN+FRfdMO 8K/A== X-Gm-Message-State: ABuFfojQTA/c8MnQ6cLNITCDcVq4872Mr91p9443CBlz6ZwtH/AcYxdS 01zkxKEdGO+O2AiMEOli+VvdUE5JqfI= X-Google-Smtp-Source: ACcGV63gCy/zVd9u6PKeC5YkKfC1pWasGlJOVOzuuyqknZctQGv8DTAAkquUVj+sI6+T+ijtty4GxA== X-Received: by 2002:a17:902:54d:: with SMTP id 71-v6mr23475015plf.80.1539887282442; Thu, 18 Oct 2018 11:28:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 11:27:56 -0700 Message-Id: <20181018182758.18646-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181018182758.18646-1-richard.henderson@linaro.org> References: <20181018182758.18646-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 1/3] target/arm: Remove writefn from TTBR0_EL3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The EL3 version of this register does not include an ASID, and so the tlb_flush performed by vmsa_ttbr_write is not needed. Signed-off-by: Richard Henderson Reviewed-by: Aaron Lindsay --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e3946562aa..24bbde4f76 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4214,7 +4214,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.mvbar) }, { .name =3D "TTBR0_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL3_RW, .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[3]) }, { .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, --=20 2.17.2 From nobody Wed May 1 23:03:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539887398824417.03696174372783; Thu, 18 Oct 2018 11:29:58 -0700 (PDT) Received: from localhost ([::1]:43769 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDD3P-0002tZ-Ig for importer@patchew.org; Thu, 18 Oct 2018 14:29:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37329) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDD1i-000232-EL for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:28:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDD1h-00009o-H5 for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:28:06 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:34664) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gDD1h-00007D-8O for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:28:05 -0400 Received: by mail-pf1-x444.google.com with SMTP id f78-v6so9506366pfe.1 for ; Thu, 18 Oct 2018 11:28:05 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id d187-v6sm4795738pfc.13.2018.10.18.11.28.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 11:28:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D3wqGudfW+0khCsxkoB/kpathOtA+AYb9IQL2BiwWuM=; b=OCOSZhuiJguo8ReanZXRLIdlQmkqF0IqpJE9u/OOkznwn39Wmv7sLvUJRtkPwqNd2E MMwmOKsjG9SSk8yusWeMJJH5GyVD1rZGfMJvl5YuJijV19nIN2pksuj4HJjzTN8cGM6N uRXkDPn1UahtXGGPU8nSts4gAR+IjlDdxhROY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D3wqGudfW+0khCsxkoB/kpathOtA+AYb9IQL2BiwWuM=; b=ATws+F4KEJhWC85XY2JwqPIvzrUxaO8TQeLgChiFYpTRmqY1ayNhUIXSGnsktL+yZs Bw2at+9Msa1RL9C3hy937tQN9nXWH6VQQEIlqeVJz6Scc/iNz5U4Y7gZ7gIUA6pztnHU UjeOsYiRJypq/CDGz/aqP7b/0o3i5KzIa16y2VTWrhJeOWCSqfAHYNPFPkuP0tE4M9ck n589KtwwSdwLRgEZwKA/Zz9tIE8AV3FFyl48lsXoaBzSh/vECdiat2BTmfiI1fuXpgKR F0PGBYQGl6L5IGm0KvrKC+dJKIwwcc4LH0rh7/k42jgBTS4Gp+MkkEO5VqKOAw0K4XFM QR4A== X-Gm-Message-State: ABuFfogL3DdThMCF9IN5PQTLNWagTZ9+3els9eqqdFr5ZdWS4rJk1sP5 9u+/mY75q7jIxKD5DSBQ50qe5DnviYs= X-Google-Smtp-Source: ACcGV61rZjP7ziE0s5e6hSu8zi8D2dM1kA0ZORtCJOgO8EU2h76/hnvRCZtuP4r5nIyZ+nc5S9F6GQ== X-Received: by 2002:a63:f448:: with SMTP id p8-v6mr29349523pgk.124.1539887283899; Thu, 18 Oct 2018 11:28:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 11:27:57 -0700 Message-Id: <20181018182758.18646-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181018182758.18646-1-richard.henderson@linaro.org> References: <20181018182758.18646-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 2/3] target/arm: Only flush tlb if ASID changes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since QEMU does not implement ASIDs, changes to the ASID must flush the tlb. However, if the ASID does not change there is no reason to flush. In testing a boot of the Ubuntu installer to the first menu, this reduces the number of flushes by 30%, or nearly 600k instances. Signed-off-by: Richard Henderson Reviewed-by: Aaron Lindsay --- target/arm/helper.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 24bbde4f76..ed70ac645e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2709,12 +2709,10 @@ static void vmsa_tcr_el1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* 64 bit accesses to the TTBRs can change the ASID and so we - * must flush the TLB. - */ - if (cpreg_field_is_64bit(ri)) { + /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ + if (cpreg_field_is_64bit(ri) && + extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { ARMCPU *cpu =3D arm_env_get_cpu(env); - tlb_flush(CPU(cpu)); } raw_write(env, ri, value); --=20 2.17.2 From nobody Wed May 1 23:03:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539887398904708.8672580894272; Thu, 18 Oct 2018 11:29:58 -0700 (PDT) Received: from localhost ([::1]:43770 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDD3T-0002wN-7J for importer@patchew.org; Thu, 18 Oct 2018 14:29:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDD1k-00023p-9F for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:28:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDD1i-0000EJ-WD for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:28:08 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:35743) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gDD1i-0000C5-LS for qemu-devel@nongnu.org; Thu, 18 Oct 2018 14:28:06 -0400 Received: by mail-pl1-x642.google.com with SMTP id f8-v6so14709715plb.2 for ; Thu, 18 Oct 2018 11:28:06 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id d187-v6sm4795738pfc.13.2018.10.18.11.28.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 11:28:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ivNiql6u6gG8SOjY6K8rzKNCwFBL7QEcg4GjVI+RHRU=; b=THu/Fn7X9x+6tThS+pgyJGs6+en5RmB3xuT38cwWSNYl7nfddP7iaidIvXt3VUxi92 yFdA9h7/tqouFKhyMWTKuaqYsEpbMuv2pHHtwNSOIhaE+/lHn8VBvpzmrA/5SDsFAT19 4OLW+Ub10l90O17BLD5hyPmf5ojCQgtzxHiKg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ivNiql6u6gG8SOjY6K8rzKNCwFBL7QEcg4GjVI+RHRU=; b=G1XGotfgMp7srRFQRCEE2IsKyFlMO+iHdklkuS3IkfUo+MUSdeKGEJ11lLMGP6j/v3 nrqPYRhxnLux+NUFyxDF6CPsry4Cz10jKwUESeTBJdL7hcOSqOlBsNDgq0KxwSY/P5bC C9L42NSBkxkrE5P9kFT/pAakm8tWoGa6YXsloFwRdZOVEwupMLoYJMAZa81xcXvri5Uh Y921evD++MBj/VV3jptHTMhU6T7/zlbOtVeV/XIPXPWIDv/oc4s64weUQkpJxEWucZDN zSHVfEiY+7tgRB0JB+qIQC5MR+zo85Wa8Qf+IeTw2zv6Hc23TYk7VId9bWXKTsqrIY/M nN5g== X-Gm-Message-State: ABuFfoizD0+/sFiASCTqGZ1ZfNu3icKr6xXK4p0yK1a9+xNVE1cVrx/L 22KWtBJ/rYXHpJL0Ejn1oXNWy76tiE4= X-Google-Smtp-Source: ACcGV62UUWCrpUuH8dQLvaiZE3DNQsgXVG4EYuYYqrY/OJhYYdf/sT8tIf+/RvgQSMaLhQcBH0Xx6A== X-Received: by 2002:a17:902:7802:: with SMTP id p2-v6mr30450727pll.170.1539887285238; Thu, 18 Oct 2018 11:28:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 11:27:58 -0700 Message-Id: <20181018182758.18646-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181018182758.18646-1-richard.henderson@linaro.org> References: <20181018182758.18646-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH 3/3] target/arm: Flush only the TLBs affected by TTBR*_EL1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Only the EL0 and EL1 TLBs are affected by the EL1 register, so flush only 2 of the 8 TLBs. In testing a boot of the Ubuntu installer to the first menu, this accounts for nearly all of the full tlb flushes: all but 11k of the 1.2M instances without the patch. Signed-off-by: Richard Henderson --- target/arm/helper.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ed70ac645e..a943e91666 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2706,14 +2706,16 @@ static void vmsa_tcr_el1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, tcr->raw_tcr =3D value; } =20 -static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void vmsa_ttbr1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ if (cpreg_field_is_64bit(ri) && extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { ARMCPU *cpu =3D arm_env_get_cpu(env); - tlb_flush(CPU(cpu)); + tlb_flush_by_mmuidx(CPU(cpu), + ARMMMUIdxBit_S12NSE1 | + ARMMMUIdxBit_S12NSE0); } raw_write(env, ri, value); } @@ -2761,12 +2763,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr1_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .writefn =3D vmsa_ttbr1_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, @@ -3018,12 +3020,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr1_write, }, { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr1_write, }, REGINFO_SENTINEL }; =20 --=20 2.17.2