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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id a79-v6sm23094458pfa.124.2018.10.16.15.31.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 15:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YD7/9LQdh4/sUdFNONBp4cFghNNenH/BO7NE1FqcTFs=; b=UG0lfYk+dhe7bdp6Llc7rCrXN9L/zOOaR76yjlTMOqi3ZEqrQQAq7/dze3K0DaD8+w lP0wUeZZeF0eD6nK5kWVCGGgXN3xWvlkvXdBmvj7bke8bMWkvwPe366JXqd9i61J7PpR qDUz1B/HahrGxFcDWt5jFwzDDKpCYebl1RG7A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YD7/9LQdh4/sUdFNONBp4cFghNNenH/BO7NE1FqcTFs=; b=sSXebp45f6QW9W4t5WXPe5Ajv/T6MfLYKq7G60EG1f45b3X2Hw4EgX47aOne6Xwnxo AYzrRPLW8s29nNX0Rmo2AHLKjCTNElTJmntg3ChcTwsHgyR05Mr7Jla7NBHv4ZIlKJEu sxzUJAk9D9SHy3lG0G9tMmDrAhMWoO2wrCGVg3TgDngpbSLugi1q1I5y8zn/Y2IOb8z1 IBSot6zW2YxK9IwnFIfwZ+jmoshQXbJunPhiNCgcgaHvpFyRhs90SQbvhxEN30To4+vS wSb6F0pjS4b85VQEUuUmpPGK4B10ddgX4oQxDJL7y+fl7am4irz/d1gsUmbewpV0Oh9k vtGw== X-Gm-Message-State: ABuFfoi/XOuzMlkfTbJGuI7OCG+zkaBaxjZ5gjr4mYUCSZ8mLQvpxqM9 n5yvYrfNZ6BsaM6eyar+k51oOUFVGtU= X-Google-Smtp-Source: ACcGV63am1yhSc4xxhmWn+31OiCKA1TRqlYGSRrWuLbtyWQmHc6VRBkw+9qbb6qzcNQHJc/ltvenEQ== X-Received: by 2002:a62:4803:: with SMTP id v3-v6mr24707322pfa.89.1539729089867; Tue, 16 Oct 2018 15:31:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 15:31:14 -0700 Message-Id: <20181016223115.24100-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016223115.24100-1-richard.henderson@linaro.org> References: <20181016223115.24100-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 7/8] target/arm: Convert sve from feature bit to aa64pfr0 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/cpu.h | 16 +++++++++++++++- linux-user/aarch64/signal.c | 4 ++-- linux-user/elfload.c | 2 +- linux-user/syscall.c | 10 ++++++---- target/arm/cpu64.c | 5 ++++- target/arm/helper.c | 9 ++++++--- target/arm/machine.c | 3 +-- target/arm/translate-a64.c | 4 ++-- 8 files changed, 37 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index af68932946..3ebf79745b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1537,6 +1537,16 @@ FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) FIELD(ID_AA64ISAR1, SB, 36, 4) FIELD(ID_AA64ISAR1, SPECRES, 40, 4) =20 +FIELD(ID_AA64PFR0, EL0, 0, 4) +FIELD(ID_AA64PFR0, EL1, 4, 4) +FIELD(ID_AA64PFR0, EL2, 8, 4) +FIELD(ID_AA64PFR0, EL3, 12, 4) +FIELD(ID_AA64PFR0, FP, 16, 4) +FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) +FIELD(ID_AA64PFR0, GIC, 24, 4) +FIELD(ID_AA64PFR0, RAS, 28, 4) +FIELD(ID_AA64PFR0, SVE, 32, 4) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF @@ -1585,7 +1595,6 @@ enum arm_features { ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ - ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ }; @@ -3269,6 +3278,11 @@ static inline bool isar_feature_aa64_fcma(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; } =20 +static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 07fedfc33c..f84a9cf28a 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -314,7 +314,7 @@ static int target_restore_sigframe(CPUARMState *env, break; =20 case TARGET_SVE_MAGIC: - if (arm_feature(env, ARM_FEATURE_SVE)) { + if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) { vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); if (!sve && size =3D=3D sve_size) { @@ -433,7 +433,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, &layout); =20 /* SVE state needs saving only if it exists. */ - if (arm_feature(env, ARM_FEATURE_SVE)) { + if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) { vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); sve_ofs =3D alloc_sigframe_space(sve_size, &layout); diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c6edc545ac..64e41fb235 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -593,7 +593,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM); GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP); GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA); - GET_FEATURE(ARM_FEATURE_SVE, ARM_HWCAP_A64_SVE); + GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE); =20 #undef GET_FEATURE #undef GET_FEATURE_ID diff --git a/linux-user/syscall.c b/linux-user/syscall.c index ae3c0dfef7..48567a4416 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9356,7 +9356,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, * even though the current architectural maximum is VQ=3D16. */ ret =3D -TARGET_EINVAL; - if (arm_feature(cpu_env, ARM_FEATURE_SVE) + if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(cpu_env)) && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { CPUARMState *env =3D cpu_env; ARMCPU *cpu =3D arm_env_get_cpu(env); @@ -9375,9 +9375,11 @@ static abi_long do_syscall1(void *cpu_env, int num, = abi_long arg1, return ret; case TARGET_PR_SVE_GET_VL: ret =3D -TARGET_EINVAL; - if (arm_feature(cpu_env, ARM_FEATURE_SVE)) { - CPUARMState *env =3D cpu_env; - ret =3D ((env->vfp.zcr_el[1] & 0xf) + 1) * 16; + { + ARMCPU *cpu =3D arm_env_get_cpu(cpu_env); + if (cpu_isar_feature(aa64_sve, cpu)) { + ret =3D ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + } } return ret; #endif /* AARCH64 */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eb5aba4870..0520a42196 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -318,6 +318,10 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); cpu->isar.id_aa64isar1 =3D t; =20 + t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); + cpu->isar.id_aa64pfr0 =3D t; + /* Replicate the same data to the 32-bit id registers. */ u =3D cpu->isar.id_isar5; u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ @@ -340,7 +344,6 @@ static void aarch64_max_initfn(Object *obj) * present in either. */ set_feature(&cpu->env, ARM_FEATURE_V8_FP16); - set_feature(&cpu->env, ARM_FEATURE_SVE); /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index b7d9a3392e..0685c9bc93 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5618,7 +5618,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &sctlr); } =20 - if (arm_feature(env, ARM_FEATURE_SVE)) { + if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); @@ -12671,13 +12671,15 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, uint32_t flags; =20 if (is_a64(env)) { + ARMCPU *cpu =3D arm_env_get_cpu(env); + *pc =3D env->pc; flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; /* Get control bits for tagged addresses */ flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT= ); flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); =20 - if (arm_feature(env, ARM_FEATURE_SVE)) { + if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); uint32_t zcr_len; =20 @@ -12801,11 +12803,12 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsi= gned vq) void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64) { + ARMCPU *cpu =3D arm_env_get_cpu(env); int old_len, new_len; bool old_a64, new_a64; =20 /* Nothing to do if no SVE. */ - if (!arm_feature(env, ARM_FEATURE_SVE)) { + if (!cpu_isar_feature(aa64_sve, cpu)) { return; } =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 5402ff8ae5..feeb91dc0a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -131,9 +131,8 @@ static const VMStateDescription vmstate_iwmmxt =3D { static bool sve_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_SVE); + return cpu_isar_feature(aa64_sve, cpu); } =20 /* The first two words of each Zreg is stored in VFP state. */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5979ba4778..3feb786007 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -173,7 +173,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, " FPCR=3D%08x FPSR=3D%08x\n", vfp_get_fpcr(env), vfp_get_fpsr(env)); =20 - if (arm_feature(env, ARM_FEATURE_SVE) && sve_exception_el(env, el) =3D= =3D 0) { + if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { int j, zcr_len =3D sve_zcr_len_for_el(env, el); =20 for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { @@ -13790,7 +13790,7 @@ static void disas_a64_insn(CPUARMState *env, DisasC= ontext *s) unallocated_encoding(s); break; case 0x2: - if (!arm_dc_feature(s, ARM_FEATURE_SVE) || !disas_sve(s, insn)) { + if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { unallocated_encoding(s); } break; --=20 2.17.2