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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id a79-v6sm23094458pfa.124.2018.10.16.15.31.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 15:31:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tPt2b6vHu83/KVV1oPQBHxI6axfXRsFslZXK1O07DV8=; b=OT99HvxyPyUtWb+P8mCdV6qDEjf8hp6ae98hpojk8Nr1dxUMAuqpeSARCIE2BOq353 N9auPGrTUUAm+7zCJzEbq7Yn5s1OViUJZsf1XXUQWbIIWQKrte22wgfajVjRpyfrWUwo H9axaAS06s4qSCzT4ixpf13rZOJ6OV1aH6zIA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tPt2b6vHu83/KVV1oPQBHxI6axfXRsFslZXK1O07DV8=; b=O/TVSA1DLSfqx58kwzsjFXwgs4Fwo/7TK/zlUGvjRZk5JzIpBEEcSnhJQTDbwC08HQ ObURH4om+a7Jb+zyeP3udQoZy2aKWtNUbNiMETPpxJbk8JvW95sdYN9jJl+O0yG1PkqF 3aB7Y/XqD8Q7a1eErh84a0NsU8u9FBVztdsuTRr24bjaN1vNgiHsegtlYDZf3DtC6IPZ v9WNaimARMVZifEWLN7s4as7WNcDm/+UCGE+uty+IAkCObdLPzn+42bmH48rzcFvfxgE +0SsR5fbtnVfCvzaemV77lub95vTRyUd1XC1GJBmX4zUgAB5oEhBk2NL6Tp5sRxxErVU 3uUQ== X-Gm-Message-State: ABuFfoj0RPJUd4P2QyFZ7XlZlPvePK5AqD6rQ9bRoMFvdHX1leKI6llO cQn5t2M+QGbf91/kcWK+ddoTm4kR9dg= X-Google-Smtp-Source: ACcGV60mP+wfzlWtS6gGQvXySCygbCLwVYyLziiHMHq7/LX/3Fmaybei6rFNFMib7AwXHKIvxKqHDg== X-Received: by 2002:a63:30c8:: with SMTP id w191-v6mr21617979pgw.447.1539729088323; Tue, 16 Oct 2018 15:31:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 15:31:13 -0700 Message-Id: <20181016223115.24100-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016223115.24100-1-richard.henderson@linaro.org> References: <20181016223115.24100-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v4 6/8] target/arm: Convert t32ee from feature bit to isar3 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 +++++- linux-user/elfload.c | 2 +- target/arm/cpu.c | 4 ---- target/arm/helper.c | 2 +- target/arm/machine.c | 3 +-- 5 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4fdace5de1..af68932946 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1558,7 +1558,6 @@ enum arm_features { ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE, ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ ARM_FEATURE_V4T, @@ -3157,6 +3156,11 @@ static inline bool isar_feature_jazelle(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; } =20 +static inline bool isar_feature_t32ee(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar3, ID_ISAR3, T32EE) !=3D 0; +} + static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) !=3D 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1e0f22d812..c6edc545ac 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -466,7 +466,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); - GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + GET_FEATURE_ID(t32ee, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8f16e96b6c..e08a2d2d79 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1440,7 +1440,6 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr =3D 0x410fc080; @@ -1509,7 +1508,6 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different @@ -1572,7 +1570,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); @@ -1618,7 +1615,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); diff --git a/target/arm/helper.c b/target/arm/helper.c index 342c802a95..b7d9a3392e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5359,7 +5359,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + if (cpu_isar_feature(t32ee, cpu)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { diff --git a/target/arm/machine.c b/target/arm/machine.c index ff4ec22bf7..5402ff8ae5 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -301,9 +301,8 @@ static const VMStateDescription vmstate_m =3D { static bool thumb2ee_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_THUMB2EE); + return cpu_isar_feature(t32ee, cpu); } =20 static const VMStateDescription vmstate_thumb2ee =3D { --=20 2.17.2